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drm/amd/pm: Update pci link speed for smu v13.0.6

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Update pcie link speed registers for smu v13.0.6 &
populate gpu metric table with pcie link speed rather than
gen for smu v13_0_0, smu v13_0_6 & smu v13_0_7

v2:
Update ESM register address
Used macro to convert pcie gen to speed

v3:
Chaged macro to inline function for pcie gen to speed

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Asad Kamal
2023-08-10 22:08:40 +08:00
committed by Alex Deucher
parent e49311c44a
commit f1d1abd616
7 changed files with 36 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
View File

@ -64,7 +64,6 @@
#define LINK_SPEED_MAX 3
static const __maybe_unused uint16_t link_width[] = {0, 1, 2, 4, 8, 12, 16};
static const __maybe_unused uint16_t link_speed[] = {25, 50, 80, 160};
static const
struct smu_temperature_range __maybe_unused smu11_thermal_policy[] = {

1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
View File

@ -83,7 +83,6 @@ MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin");
#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
static const int link_speed[] = {25, 50, 80, 160};
const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5};
const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};

7
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
View File

@ -102,6 +102,8 @@
#define PP_OD_FEATURE_UCLK_FMAX 3
#define PP_OD_FEATURE_GFX_VF_CURVE 4
#define LINK_SPEED_MAX 3
static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
@ -1760,7 +1762,10 @@ static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu,
gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
gpu_metrics->pcie_link_width = metrics->PcieWidth;
gpu_metrics->pcie_link_speed = metrics->PcieRate;
if ((metrics->PcieRate - 1) > LINK_SPEED_MAX)
gpu_metrics->pcie_link_speed = pcie_gen_to_speed(1);
else
gpu_metrics->pcie_link_speed = pcie_gen_to_speed(metrics->PcieRate);
gpu_metrics->system_clock_counter = ktime_get_boottime_ns();

16
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
View File

@ -80,12 +80,17 @@
/* possible frequency drift (1Mhz) */
#define EPSILON 1
#define smnPCIE_ESM_CTRL 0x193D0
#define smnPCIE_ESM_CTRL 0x93D0
#define smnPCIE_LC_LINK_WIDTH_CNTL 0x1a340288
#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
#define MAX_LINK_WIDTH 6
#define smnPCIE_LC_SPEED_CNTL 0x1a340290
#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xE0
#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5
#define LINK_SPEED_MAX 4
static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
@ -1930,6 +1935,7 @@ smu_v13_0_6_get_current_pcie_link_width_level(struct smu_context *smu)
static int smu_v13_0_6_get_current_pcie_link_speed(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
uint32_t speed_level;
uint32_t esm_ctrl;
/* TODO: confirm this on real target */
@ -1937,7 +1943,13 @@ static int smu_v13_0_6_get_current_pcie_link_speed(struct smu_context *smu)
if ((esm_ctrl >> 15) & 0x1FFFF)
return (((esm_ctrl >> 8) & 0x3F) + 128);
return smu_v13_0_get_current_pcie_link_speed(smu);
speed_level = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
>> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
if (speed_level > LINK_SPEED_MAX)
speed_level = 0;
return pcie_gen_to_speed(speed_level + 1);
}
static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table)

7
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
View File

@ -78,6 +78,8 @@
#define PP_OD_FEATURE_UCLK_FMAX 3
#define PP_OD_FEATURE_GFX_VF_CURVE 4
#define LINK_SPEED_MAX 3
static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
@ -1736,7 +1738,10 @@ static ssize_t smu_v13_0_7_get_gpu_metrics(struct smu_context *smu,
gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
gpu_metrics->pcie_link_width = metrics->PcieWidth;
gpu_metrics->pcie_link_speed = metrics->PcieRate;
if ((metrics->PcieRate - 1) > LINK_SPEED_MAX)
gpu_metrics->pcie_link_speed = pcie_gen_to_speed(1);
else
gpu_metrics->pcie_link_speed = pcie_gen_to_speed(metrics->PcieRate);
gpu_metrics->system_clock_counter = ktime_get_boottime_ns();

2
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
View File

@ -39,6 +39,8 @@
#define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
const int link_speed[] = {25, 50, 80, 160, 320, 640};
#undef __SMU_DUMMY_MAP
#define __SMU_DUMMY_MAP(type) #type
static const char * const __smu_message_names[] = {

8
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
View File

@ -30,6 +30,14 @@
#define FDO_PWM_MODE_STATIC 1
#define FDO_PWM_MODE_STATIC_RPM 5
extern const int link_speed[];
/* Helper to Convert from PCIE Gen 1/2/3/4/5/6 to 0.1 GT/s speed units */
static inline int pcie_gen_to_speed(uint32_t gen)
{
return ((gen == 0) ? link_speed[0] : link_speed[gen - 1]);
}
int smu_cmn_send_msg_without_waiting(struct smu_context *smu,
uint16_t msg_index,
uint32_t param);