ASoC: SOF: Intel: mtl/lnl: Improve firmware boot state
Merge series from Peter Ujfalusi <peter.ujfalusi@linux.intel.com>: This series improves the firmware/boot state handling which will allow failed IMR boot recovery and human readable boot failure decoding. Additionally a new debugfs file is added to force a purge/clean boot of the DSP for developers.
This commit is contained in:
Mark Brown
commit
f79b1758b8
@ -15,6 +15,7 @@
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* Hardware interface for HDA DSP code loader
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*/
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#include <linux/debugfs.h>
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#include <linux/firmware.h>
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#include <sound/hdaudio_ext.h>
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#include <sound/hda_register.h>
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@ -643,8 +644,12 @@ int hda_dsp_post_fw_run(struct snd_sof_dev *sdev)
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/* Check if IMR boot is usable */
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if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT) &&
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(sdev->fw_ready.flags & SOF_IPC_INFO_D3_PERSISTENT ||
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sdev->pdata->ipc_type == SOF_IPC_TYPE_4))
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sdev->pdata->ipc_type == SOF_IPC_TYPE_4)) {
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hdev->imrboot_supported = true;
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debugfs_create_bool("skip_imr_boot",
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0644, sdev->debugfs_root,
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&hdev->skip_imr_boot);
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}
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}
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hda_sdw_int_enable(sdev, true);
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@ -19,6 +19,7 @@
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#include <sound/hda_register.h>
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#include <linux/acpi.h>
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#include <linux/debugfs.h>
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#include <linux/module.h>
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#include <linux/soundwire/sdw.h>
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#include <linux/soundwire/sdw_intel.h>
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@ -34,6 +35,7 @@
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#include "../ipc4-topology.h"
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#include "hda.h"
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#include "telemetry.h"
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#include "mtl.h"
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#define CREATE_TRACE_POINTS
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#include <trace/events/sof_intel.h>
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@ -596,7 +598,7 @@ static const struct hda_dsp_msg_code hda_dsp_rom_fw_error_texts[] = {
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};
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#define FSR_ROM_STATE_ENTRY(state) {FSR_STATE_ROM_##state, #state}
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static const struct hda_dsp_msg_code fsr_rom_state_names[] = {
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static const struct hda_dsp_msg_code cavs_fsr_rom_state_names[] = {
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FSR_ROM_STATE_ENTRY(INIT),
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FSR_ROM_STATE_ENTRY(INIT_DONE),
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FSR_ROM_STATE_ENTRY(CSE_MANIFEST_LOADED),
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@ -619,6 +621,58 @@ static const struct hda_dsp_msg_code fsr_rom_state_names[] = {
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FSR_ROM_STATE_ENTRY(CSE_IPC_DOWN),
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};
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static const struct hda_dsp_msg_code ace_fsr_rom_state_names[] = {
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FSR_ROM_STATE_ENTRY(INIT),
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FSR_ROM_STATE_ENTRY(INIT_DONE),
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FSR_ROM_STATE_ENTRY(CSE_MANIFEST_LOADED),
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FSR_ROM_STATE_ENTRY(FW_MANIFEST_LOADED),
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FSR_ROM_STATE_ENTRY(FW_FW_LOADED),
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FSR_ROM_STATE_ENTRY(FW_ENTERED),
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FSR_ROM_STATE_ENTRY(VERIFY_FEATURE_MASK),
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FSR_ROM_STATE_ENTRY(GET_LOAD_OFFSET),
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FSR_ROM_STATE_ENTRY(RESET_VECTOR_DONE),
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FSR_ROM_STATE_ENTRY(PURGE_BOOT),
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FSR_ROM_STATE_ENTRY(RESTORE_BOOT),
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FSR_ROM_STATE_ENTRY(FW_ENTRY_POINT),
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FSR_ROM_STATE_ENTRY(VALIDATE_PUB_KEY),
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FSR_ROM_STATE_ENTRY(POWER_DOWN_HPSRAM),
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FSR_ROM_STATE_ENTRY(POWER_DOWN_ULPSRAM),
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FSR_ROM_STATE_ENTRY(POWER_UP_ULPSRAM_STACK),
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FSR_ROM_STATE_ENTRY(POWER_UP_HPSRAM_DMA),
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FSR_ROM_STATE_ENTRY(BEFORE_EP_POINTER_READ),
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FSR_ROM_STATE_ENTRY(VALIDATE_MANIFEST),
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FSR_ROM_STATE_ENTRY(VALIDATE_FW_MODULE),
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FSR_ROM_STATE_ENTRY(PROTECT_IMR_REGION),
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FSR_ROM_STATE_ENTRY(PUSH_MODEL_ROUTINE),
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FSR_ROM_STATE_ENTRY(PULL_MODEL_ROUTINE),
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FSR_ROM_STATE_ENTRY(VALIDATE_PKG_DIR),
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FSR_ROM_STATE_ENTRY(VALIDATE_CPD),
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FSR_ROM_STATE_ENTRY(VALIDATE_CSS_MAN_HEADER),
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FSR_ROM_STATE_ENTRY(VALIDATE_BLOB_SVN),
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FSR_ROM_STATE_ENTRY(VERIFY_IFWI_PARTITION),
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FSR_ROM_STATE_ENTRY(REMOVE_ACCESS_CONTROL),
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FSR_ROM_STATE_ENTRY(AUTH_BYPASS),
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FSR_ROM_STATE_ENTRY(AUTH_ENABLED),
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FSR_ROM_STATE_ENTRY(INIT_DMA),
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FSR_ROM_STATE_ENTRY(PURGE_FW_ENTRY),
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FSR_ROM_STATE_ENTRY(PURGE_FW_END),
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FSR_ROM_STATE_ENTRY(CLEAN_UP_BSS_DONE),
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FSR_ROM_STATE_ENTRY(IMR_RESTORE_ENTRY),
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FSR_ROM_STATE_ENTRY(IMR_RESTORE_END),
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FSR_ROM_STATE_ENTRY(FW_MANIFEST_IN_DMA_BUFF),
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FSR_ROM_STATE_ENTRY(LOAD_CSE_MAN_TO_IMR),
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FSR_ROM_STATE_ENTRY(LOAD_FW_MAN_TO_IMR),
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FSR_ROM_STATE_ENTRY(LOAD_FW_CODE_TO_IMR),
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FSR_ROM_STATE_ENTRY(FW_LOADING_DONE),
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FSR_ROM_STATE_ENTRY(FW_CODE_LOADED),
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FSR_ROM_STATE_ENTRY(VERIFY_IMAGE_TYPE),
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FSR_ROM_STATE_ENTRY(AUTH_API_INIT),
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FSR_ROM_STATE_ENTRY(AUTH_API_PROC),
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FSR_ROM_STATE_ENTRY(AUTH_API_FIRST_BUSY),
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FSR_ROM_STATE_ENTRY(AUTH_API_FIRST_RESULT),
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FSR_ROM_STATE_ENTRY(AUTH_API_CLEANUP),
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};
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#define FSR_BRINGUP_STATE_ENTRY(state) {FSR_STATE_BRINGUP_##state, #state}
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static const struct hda_dsp_msg_code fsr_bringup_state_names[] = {
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FSR_BRINGUP_STATE_ENTRY(INIT),
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@ -663,7 +717,7 @@ hda_dsp_get_state_text(u32 code, const struct hda_dsp_msg_code *msg_code,
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return NULL;
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}
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static void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level)
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void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level)
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{
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const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata);
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const char *state_text, *error_text, *module_text;
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@ -679,12 +733,19 @@ static void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level)
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else
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module_text = fsr_module_names[module];
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if (module == FSR_MOD_BRNGUP)
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if (module == FSR_MOD_BRNGUP) {
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state_text = hda_dsp_get_state_text(state, fsr_bringup_state_names,
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ARRAY_SIZE(fsr_bringup_state_names));
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else
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state_text = hda_dsp_get_state_text(state, fsr_rom_state_names,
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ARRAY_SIZE(fsr_rom_state_names));
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} else {
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if (chip->hw_ip_version < SOF_INTEL_ACE_1_0)
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state_text = hda_dsp_get_state_text(state,
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cavs_fsr_rom_state_names,
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ARRAY_SIZE(cavs_fsr_rom_state_names));
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else
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state_text = hda_dsp_get_state_text(state,
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ace_fsr_rom_state_names,
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ARRAY_SIZE(ace_fsr_rom_state_names));
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}
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/* not for us, must be generic sof message */
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if (!state_text) {
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@ -695,6 +695,8 @@ int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
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irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
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int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
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void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level);
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/*
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* DSP Code loader.
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*/
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@ -6,6 +6,7 @@
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* Hardware interface for audio DSP on LunarLake.
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*/
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#include <linux/debugfs.h>
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#include <linux/firmware.h>
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#include <sound/hda_register.h>
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#include <sound/sof/ipc4/header.h>
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@ -16,6 +17,7 @@
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#include "hda-ipc.h"
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#include "../sof-audio.h"
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#include "mtl.h"
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#include "lnl.h"
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#include <sound/hda-mlink.h>
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/* LunarLake ops */
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@ -83,8 +85,12 @@ static int lnl_dsp_post_fw_run(struct snd_sof_dev *sdev)
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
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/* Check if IMR boot is usable */
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if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT))
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if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT)) {
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hda->imrboot_supported = true;
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debugfs_create_bool("skip_imr_boot",
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0644, sdev->debugfs_root,
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&hda->skip_imr_boot);
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}
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}
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return 0;
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@ -192,7 +198,7 @@ const struct sof_intel_dsp_desc lnl_chip_info = {
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.ipc_ack = MTL_DSP_REG_HFIPCXIDA,
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.ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
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.ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
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.rom_status_reg = MTL_DSP_ROM_STS,
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.rom_status_reg = LNL_DSP_REG_HFDSC,
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.rom_init_timeout = 300,
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.ssp_count = MTL_SSP_COUNT,
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.d0i3_offset = MTL_HDA_VS_D0I3C,
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15
sound/soc/sof/intel/lnl.h
Normal file
15
sound/soc/sof/intel/lnl.h
Normal file
@ -0,0 +1,15 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* Copyright(c) 2024 Intel Corporation. All rights reserved.
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*/
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#ifndef __SOF_INTEL_LNL_H
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#define __SOF_INTEL_LNL_H
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#define LNL_DSP_REG_HFDSC 0x160200 /* DSP core0 status */
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#define LNL_DSP_REG_HFDEC 0x160204 /* DSP core0 error */
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#endif /* __SOF_INTEL_LNL_H */
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@ -9,6 +9,7 @@
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* Hardware interface for audio DSP on Meteorlake.
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*/
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#include <linux/debugfs.h>
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#include <linux/firmware.h>
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#include <sound/sof/ipc4/header.h>
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#include <trace/events/sof_intel.h>
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@ -294,8 +295,12 @@ int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev)
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}
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/* Check if IMR boot is usable */
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if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT))
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if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT)) {
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hdev->imrboot_supported = true;
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debugfs_create_bool("skip_imr_boot",
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0644, sdev->debugfs_root,
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&hdev->skip_imr_boot);
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}
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}
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hda_sdw_int_enable(sdev, true);
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@ -305,22 +310,16 @@ int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev)
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void mtl_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
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{
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char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR;
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u32 romdbgsts;
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u32 romdbgerr;
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u32 fwsts;
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u32 fwlec;
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hda_dsp_get_state(sdev, level);
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fwsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_STS);
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fwlec = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_ERROR);
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romdbgsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY);
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romdbgerr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY_ERROR);
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dev_err(sdev->dev, "ROM status: %#x, ROM error: %#x\n", fwsts, fwlec);
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dev_err(sdev->dev, "ROM debug status: %#x, ROM debug error: %#x\n", romdbgsts,
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romdbgerr);
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romdbgsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY + 0x8 * 3);
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dev_printk(level, sdev->dev, "ROM feature bit%s enabled\n",
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romdbgsts & BIT(24) ? "" : " not");
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if (fwsts != 0xffffffff)
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dev_err(sdev->dev, "Firmware state: %#x, status/error code: %#x\n",
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fwsts, fwlec);
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sof_ipc4_intel_dump_telemetry_state(sdev, flags);
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}
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@ -439,7 +438,7 @@ int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
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{
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
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const struct sof_intel_dsp_desc *chip = hda->desc;
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unsigned int status;
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unsigned int status, target_status;
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u32 ipc_hdr, flags;
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char *dump_msg;
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int ret;
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@ -485,13 +484,40 @@ int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
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mtl_enable_ipc_interrupts(sdev);
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/*
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* ACE workaround: don't wait for ROM INIT.
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* The platform cannot catch ROM_INIT_DONE because of a very short
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* timing window. Follow the recommendations and skip this part.
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*/
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if (chip->rom_status_reg == MTL_DSP_ROM_STS) {
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/*
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* Workaround: when the ROM status register is pointing to
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* the SRAM window (MTL_DSP_ROM_STS) the platform cannot catch
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* ROM_INIT_DONE because of a very short timing window.
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* Follow the recommendations and skip target state waiting.
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*/
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return 0;
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}
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return 0;
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/*
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* step 7:
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* - Cold/Full boot: wait for ROM init to proceed to download the firmware
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* - IMR boot: wait for ROM firmware entered (firmware booted up from IMR)
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*/
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if (imr_boot)
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target_status = FSR_STATE_FW_ENTERED;
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else
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target_status = FSR_STATE_INIT_DONE;
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ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
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chip->rom_status_reg, status,
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(FSR_TO_STATE_CODE(status) == target_status),
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HDA_DSP_REG_POLL_INTERVAL_US,
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chip->rom_init_timeout *
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USEC_PER_MSEC);
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if (!ret)
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return 0;
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if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
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dev_err(sdev->dev,
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"%s: timeout with rom_status_reg (%#x) read\n",
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__func__, chip->rom_status_reg);
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err:
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flags = SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX | SOF_DBG_DUMP_OPTIONAL;
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@ -503,6 +529,7 @@ err:
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dump_msg = kasprintf(GFP_KERNEL, "Boot iteration failed: %d/%d",
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hda->boot_iteration, HDA_FW_BOOT_ATTEMPTS);
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snd_sof_dsp_dbg_dump(sdev, dump_msg, flags);
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mtl_enable_interrupts(sdev, false);
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mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE);
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kfree(dump_msg);
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@ -727,7 +754,7 @@ const struct sof_intel_dsp_desc mtl_chip_info = {
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.ipc_ack = MTL_DSP_REG_HFIPCXIDA,
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.ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
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.ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
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.rom_status_reg = MTL_DSP_ROM_STS,
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.rom_status_reg = MTL_DSP_REG_HFFLGPXQWY,
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.rom_init_timeout = 300,
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.ssp_count = MTL_SSP_COUNT,
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.ssp_base_offset = CNL_SSP_BASE_OFFSET,
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@ -755,7 +782,7 @@ const struct sof_intel_dsp_desc arl_s_chip_info = {
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.ipc_ack = MTL_DSP_REG_HFIPCXIDA,
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.ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
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.ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
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.rom_status_reg = MTL_DSP_ROM_STS,
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.rom_status_reg = MTL_DSP_REG_HFFLGPXQWY,
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.rom_init_timeout = 300,
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.ssp_count = MTL_SSP_COUNT,
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.ssp_base_offset = CNL_SSP_BASE_OFFSET,
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@ -70,8 +70,52 @@
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#define MTL_DSP_ROM_STS MTL_SRAM_WINDOW_OFFSET(0) /* ROM status */
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#define MTL_DSP_ROM_ERROR (MTL_SRAM_WINDOW_OFFSET(0) + 0x4) /* ROM error code */
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#define MTL_DSP_REG_HFFLGPXQWY 0x163200 /* ROM debug status */
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#define MTL_DSP_REG_HFFLGPXQWY_ERROR 0x163204 /* ROM debug error code */
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#define MTL_DSP_REG_HFFLGPXQWY 0x163200 /* DSP core0 status */
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#define MTL_DSP_REG_HFFLGPXQWY_ERROR 0x163204 /* DSP core0 error */
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/* FSR status codes */
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#define FSR_STATE_ROM_RESET_VECTOR_DONE 0x8
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#define FSR_STATE_ROM_PURGE_BOOT 0x9
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#define FSR_STATE_ROM_RESTORE_BOOT 0xA
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#define FSR_STATE_ROM_FW_ENTRY_POINT 0xB
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#define FSR_STATE_ROM_VALIDATE_PUB_KEY 0xC
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#define FSR_STATE_ROM_POWER_DOWN_HPSRAM 0xD
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#define FSR_STATE_ROM_POWER_DOWN_ULPSRAM 0xE
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#define FSR_STATE_ROM_POWER_UP_ULPSRAM_STACK 0xF
|
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#define FSR_STATE_ROM_POWER_UP_HPSRAM_DMA 0x10
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#define FSR_STATE_ROM_BEFORE_EP_POINTER_READ 0x11
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#define FSR_STATE_ROM_VALIDATE_MANIFEST 0x12
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#define FSR_STATE_ROM_VALIDATE_FW_MODULE 0x13
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#define FSR_STATE_ROM_PROTECT_IMR_REGION 0x14
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#define FSR_STATE_ROM_PUSH_MODEL_ROUTINE 0x15
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#define FSR_STATE_ROM_PULL_MODEL_ROUTINE 0x16
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#define FSR_STATE_ROM_VALIDATE_PKG_DIR 0x17
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#define FSR_STATE_ROM_VALIDATE_CPD 0x18
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#define FSR_STATE_ROM_VALIDATE_CSS_MAN_HEADER 0x19
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#define FSR_STATE_ROM_VALIDATE_BLOB_SVN 0x1A
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#define FSR_STATE_ROM_VERIFY_IFWI_PARTITION 0x1B
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||||
#define FSR_STATE_ROM_REMOVE_ACCESS_CONTROL 0x1C
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||||
#define FSR_STATE_ROM_AUTH_BYPASS 0x1D
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||||
#define FSR_STATE_ROM_AUTH_ENABLED 0x1E
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||||
#define FSR_STATE_ROM_INIT_DMA 0x1F
|
||||
#define FSR_STATE_ROM_PURGE_FW_ENTRY 0x20
|
||||
#define FSR_STATE_ROM_PURGE_FW_END 0x21
|
||||
#define FSR_STATE_ROM_CLEAN_UP_BSS_DONE 0x22
|
||||
#define FSR_STATE_ROM_IMR_RESTORE_ENTRY 0x23
|
||||
#define FSR_STATE_ROM_IMR_RESTORE_END 0x24
|
||||
#define FSR_STATE_ROM_FW_MANIFEST_IN_DMA_BUFF 0x25
|
||||
#define FSR_STATE_ROM_LOAD_CSE_MAN_TO_IMR 0x26
|
||||
#define FSR_STATE_ROM_LOAD_FW_MAN_TO_IMR 0x27
|
||||
#define FSR_STATE_ROM_LOAD_FW_CODE_TO_IMR 0x28
|
||||
#define FSR_STATE_ROM_FW_LOADING_DONE 0x29
|
||||
#define FSR_STATE_ROM_FW_CODE_LOADED 0x2A
|
||||
#define FSR_STATE_ROM_VERIFY_IMAGE_TYPE 0x2B
|
||||
#define FSR_STATE_ROM_AUTH_API_INIT 0x2C
|
||||
#define FSR_STATE_ROM_AUTH_API_PROC 0x2D
|
||||
#define FSR_STATE_ROM_AUTH_API_FIRST_BUSY 0x2E
|
||||
#define FSR_STATE_ROM_AUTH_API_FIRST_RESULT 0x2F
|
||||
#define FSR_STATE_ROM_AUTH_API_CLEANUP 0x30
|
||||
|
||||
#define MTL_DSP_REG_HfIMRIS1 0x162088
|
||||
#define MTL_DSP_REG_HfIMRIS1_IU_MASK BIT(0)
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user