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drm/amdgpu: Support PSP 13.0.10 on SR-IOV

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Add support for PSP 13.0.10 for SR-IOV VF

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Horace Chen <horace.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Horace Chen 2022-07-29 13:44:43 +08:00 committed by Alex Deucher
parent dc5f3829a7
commit f8bd73213a
3 changed files with 55 additions and 22 deletions
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12
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
View File

@ -328,19 +328,27 @@ static int psp_init_sriov_microcode(struct psp_context *psp)
switch (adev->ip_versions[MP0_HWIP][0]) {
case IP_VERSION(9, 0, 0):
adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
ret = psp_init_cap_microcode(psp, "vega10");
break;
case IP_VERSION(11, 0, 9):
adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
ret = psp_init_cap_microcode(psp, "navi12");
break;
case IP_VERSION(11, 0, 7):
adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
ret = psp_init_cap_microcode(psp, "sienna_cichlid");
break;
case IP_VERSION(13, 0, 2):
adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
ret = psp_init_cap_microcode(psp, "aldebaran");
ret &= psp_init_ta_microcode(psp, "aldebaran");
break;
case IP_VERSION(13, 0, 0):
adev->virt.autoload_ucode_id = 0;
break;
case IP_VERSION(13, 0, 10):
adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA;
break;
default:
BUG();
@ -768,6 +776,7 @@ static bool psp_skip_tmr(struct psp_context *psp)
case IP_VERSION(11, 0, 9):
case IP_VERSION(11, 0, 7):
case IP_VERSION(13, 0, 2):
case IP_VERSION(13, 0, 10):
return true;
default:
return false;
@ -2414,7 +2423,6 @@ static bool fw_load_skip_check(struct psp_context *psp,
if (amdgpu_sriov_vf(psp->adev) &&
amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
/*skip ucode loading in SRIOV VF */
return true;
if (psp->autoload_supported &&
@ -2488,7 +2496,7 @@ static int psp_load_non_psp_fw(struct psp_context *psp)
/* Start rlc autoload after psp recieved all the gfx firmware */
if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) {
ret = psp_rlc_autoload_start(psp);
if (ret) {
DRM_ERROR("Failed to start rlc autoload\n");

62
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
View File

@ -690,7 +690,6 @@ void amdgpu_virt_exchange_data(struct amdgpu_device *adev)
}
}
void amdgpu_detect_virtualization(struct amdgpu_device *adev)
{
uint32_t reg;
@ -811,31 +810,54 @@ enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *ad
bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id)
{
/* this version doesn't support sriov autoload */
if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 0)) {
switch (adev->ip_versions[MP0_HWIP][0]) {
case IP_VERSION(13, 0, 0):
/* no vf autoload, white list */
if (ucode_id == AMDGPU_UCODE_ID_VCN1 ||
ucode_id == AMDGPU_UCODE_ID_VCN)
return false;
else
return true;
case IP_VERSION(13, 0, 10):
/* white list */
if (ucode_id == AMDGPU_UCODE_ID_CAP
|| ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP
|| ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME
|| ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC
|| ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK
|| ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK
|| ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK
|| ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK
|| ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK
|| ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK
|| ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK
|| ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK
|| ucode_id == AMDGPU_UCODE_ID_CP_MES
|| ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA
|| ucode_id == AMDGPU_UCODE_ID_CP_MES1
|| ucode_id == AMDGPU_UCODE_ID_CP_MES1_DATA)
return false;
else
return true;
default:
/* lagacy black list */
if (ucode_id == AMDGPU_UCODE_ID_SDMA0
|| ucode_id == AMDGPU_UCODE_ID_SDMA1
|| ucode_id == AMDGPU_UCODE_ID_SDMA2
|| ucode_id == AMDGPU_UCODE_ID_SDMA3
|| ucode_id == AMDGPU_UCODE_ID_SDMA4
|| ucode_id == AMDGPU_UCODE_ID_SDMA5
|| ucode_id == AMDGPU_UCODE_ID_SDMA6
|| ucode_id == AMDGPU_UCODE_ID_SDMA7
|| ucode_id == AMDGPU_UCODE_ID_RLC_G
|| ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
|| ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
|| ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
|| ucode_id == AMDGPU_UCODE_ID_SMC)
return true;
else
return false;
}
if (ucode_id == AMDGPU_UCODE_ID_SDMA0
|| ucode_id == AMDGPU_UCODE_ID_SDMA1
|| ucode_id == AMDGPU_UCODE_ID_SDMA2
|| ucode_id == AMDGPU_UCODE_ID_SDMA3
|| ucode_id == AMDGPU_UCODE_ID_SDMA4
|| ucode_id == AMDGPU_UCODE_ID_SDMA5
|| ucode_id == AMDGPU_UCODE_ID_SDMA6
|| ucode_id == AMDGPU_UCODE_ID_SDMA7
|| ucode_id == AMDGPU_UCODE_ID_RLC_G
|| ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
|| ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
|| ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
|| ucode_id == AMDGPU_UCODE_ID_SMC)
return true;
return false;
}
void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,

3
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
View File

@ -253,6 +253,9 @@ struct amdgpu_virt {
uint32_t decode_max_frame_pixels;
uint32_t encode_max_dimension_pixels;
uint32_t encode_max_frame_pixels;
/* the ucode id to signal the autoload */
uint32_t autoload_ucode_id;
};
struct amdgpu_video_codec_info;