drm/amdgpu/vcn2.5: Remove old DPG workaround
SCRATCH2 is used to keep decode wptr as a workaround which fix a hardware DPG decode wptr update bug for vcn2.5 beforehand. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1453,11 +1453,6 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
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WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
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fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
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fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
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WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,
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RREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2) & 0x7FFFFFFF);
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fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
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/* Unstall DPG */
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WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
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0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
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@ -1519,10 +1514,6 @@ static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
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WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2,
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lower_32_bits(ring->wptr) | 0x80000000);
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if (ring->use_doorbell) {
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adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
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WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
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