drm/i915/xehp: Add compute workarounds
Additional workarounds are required once we start exposing CCS engines. Note that we have a number of workarounds that update registers in the shared render/compute reset domain. Historically we've just added such registers to the RCS engine's workaround list. But going forward we should be more careful to place such workarounds on a wa_list for an engine that definitely exists and is not fused off (e.g., a platform with no RCS would never apply the RCS wa_list). We'll keep rcs_engine_wa_init() focused on RCS-specific workarounds that only need to be applied if the RCS engine is present. A separate general_render_compute_wa_init() function will be used to define workarounds that touch registers in the shared render/compute reset domain and that we need to apply regardless of what render and/or compute engines actually exist. Any workarounds defined in this new function will internally be added to the first present RCS or CCS engine's workaround list to ensure they get applied (and only get applied once rather than being needlessly re-applied several times). Co-author: Srinivasan Shanmugam Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220301231549.1817978-13-matthew.d.roper@intel.com
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@ -1060,6 +1060,7 @@
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#define FLOW_CONTROL_ENABLE REG_BIT(15)
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#define UGM_BACKUP_MODE REG_BIT(13)
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#define MDQ_ARBITRATION_MODE REG_BIT(12)
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#define SYSTOLIC_DOP_CLOCK_GATING_DIS REG_BIT(10)
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#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE REG_BIT(8)
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#define STALL_DOP_GATING_DISABLE REG_BIT(5)
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#define THROTTLE_12_5 REG_GENMASK(4, 2)
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@ -1217,6 +1217,14 @@ gen12_emit_indirect_ctx_xcs(const struct intel_context *ce, u32 *cs)
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cs = gen12_emit_timestamp_wa(ce, cs);
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cs = gen12_emit_restore_scratch(ce, cs);
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/* Wa_16013000631:dg2 */
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if (IS_DG2_GRAPHICS_STEP(ce->engine->i915, G10, STEP_B0, STEP_C0) ||
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IS_DG2_G11(ce->engine->i915))
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if (ce->engine->class == COMPUTE_CLASS)
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cs = gen8_emit_pipe_control(cs,
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PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE,
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0);
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return cs;
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}
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@ -1921,6 +1921,11 @@ static void dg2_whitelist_build(struct intel_engine_cs *engine)
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RING_FORCE_TO_NONPRIV_RANGE_4);
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break;
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case COMPUTE_CLASS:
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/* Wa_16011157294:dg2_g10 */
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if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0))
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whitelist_reg(w, GEN9_CTX_PREEMPT_REG);
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break;
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default:
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break;
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}
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@ -2581,6 +2586,40 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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}
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}
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/*
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* The workarounds in this function apply to shared registers in
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* the general render reset domain that aren't tied to a
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* specific engine. Since all render+compute engines get reset
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* together, and the contents of these registers are lost during
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* the shared render domain reset, we'll define such workarounds
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* here and then add them to just a single RCS or CCS engine's
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* workaround list (whichever engine has the XXXX flag).
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*/
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static void
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general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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{
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struct drm_i915_private *i915 = engine->i915;
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if (IS_XEHPSDV(i915)) {
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/* Wa_1409954639 */
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wa_masked_en(wal,
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GEN8_ROW_CHICKEN,
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SYSTOLIC_DOP_CLOCK_GATING_DIS);
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/* Wa_1607196519 */
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wa_masked_en(wal,
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GEN9_ROW_CHICKEN4,
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GEN12_DISABLE_GRF_CLEAR);
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/* Wa_14010670810:xehpsdv */
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wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
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/* Wa_14010449647:xehpsdv */
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wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1,
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GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
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}
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}
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static void
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engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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{
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@ -2589,6 +2628,14 @@ engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal
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engine_fake_wa_init(engine, wal);
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/*
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* These are common workarounds that just need to applied
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* to a single RCS/CCS engine's workaround list since
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* they're reset as part of the general render domain reset.
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*/
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if (engine->class == RENDER_CLASS)
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general_render_compute_wa_init(engine, wal);
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if (engine->class == RENDER_CLASS)
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rcs_engine_wa_init(engine, wal);
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else
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