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The CPU of sun8i-r40 is powered by PMIC, let's add "cpu-supply" node.
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220517013607.2252-2-qianfanguijin@163.com
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Merge tag 'xsa-5.19-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip
Pull xen security fixes from Juergen Gross:
- XSA-403 (4 patches for blkfront and netfront drivers):
Linux Block and Network PV device frontends don't zero memory regions
before sharing them with the backend (CVE-2022-26365,
CVE-2022-33740). Additionally the granularity of the grant table
doesn't allow sharing less than a 4K page, leading to unrelated data
residing in the same 4K page as data shared with a backend being
accessible by such backend (CVE-2022-33741, CVE-2022-33742).
- XSA-405 (1 patch for netfront driver, only 5.10 and newer):
While adding logic to support XDP (eXpress Data Path), a code label
was moved in a way allowing for SKBs having references (pointers)
retained for further processing to nevertheless be freed.
- XSA-406 (1 patch for Arm specific dom0 code):
When mapping pages of guests on Arm, dom0 is using an rbtree to keep
track of the foreign mappings.
Updating of that rbtree is not always done completely with the
related lock held, resulting in a small race window, which can be
used by unprivileged guests via PV devices to cause inconsistencies
of the rbtree. These inconsistencies can lead to Denial of Service
(DoS) of dom0, e.g. by causing crashes or the inability to perform
further mappings of other guests' memory pages.
* tag 'xsa-5.19-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip:
xen/arm: Fix race in RB-tree based P2M accounting
xen-netfront: restore __skb_queue_tail() positioning in xennet_get_responses()
xen/blkfront: force data bouncing when backend is untrusted
xen/netfront: force data bouncing when backend is untrusted
xen/netfront: fix leaking data in shared pages
xen/blkfront: fix leaking data in shared pages
Add DT bindings for ST MIPID02 and DCMI to Avenger96 base DT.
Both the ST MIPID02 and DCMI are disabled by default, as the
AV96 camera module is optional.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add another mux option for RCC pin, this is used on AV96 board
for e.g. sensor clock supply.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add another mux option for DCMI pins, this is used on AV96 board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add DT for DH DRC Compact unit, which is a universal controller device.
The system has two ethernet ports, one CAN, RS485 and RS232, USB, uSD
card slot, eMMC and SDIO Wi-Fi.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add another mux option for UART5 pins, this is used on DRC Compact board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add another mux option for UART4 pins, this is used on DRC Compact board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add another mux option for UART3 pins, this is used on DRC Compact board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add another mux option for SPI2 pins, this is used on DRC Compact board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add another mux option for CAN1 pins, this is used on DRC Compact board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Those pin comments refer to SPI2 pins, not SPI1 pins, update the comments.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add UDPHS (the USB High Speed Device Port controller) support.
The both lan966x SOCs (LAN9662 and LAN9668) have the same UDPHS
IP. This IP is also the same as the one present in the SAMA5D3
SOC.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220704102845.168438-4-herve.codina@bootlin.com
Enables Reset and Clocks Controller on STM32MP13
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
According to the OSD32MP1 Power System overview[1] the EEPROM is connected to
the VDD line and not to some single-purpose fixed regulator.
Set the EEPROM supply according to the diagram to eliminate this parent-less
regulator.
[1]: https://octavosystems.com/app_notes/osd32mp1-power-system-overview/#connections
Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de>
Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
According to the OSD32MP1 Power System overview[1] ldo3's input is always
internally connected to vdd_ddr.
[1]: https://octavosystems.com/app_notes/osd32mp1-power-system-overview/#connections
Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment. No functional
changes (same DTB).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
The Buck3 on DHCOR is used to supply IO voltage. It can output either 3V3
in the default DHCOR configuration, or 2V9 in case of AV96 DHCOR variant
which has extra Empirion DCDC converter in front of the 1V8 IO supply, or
outright 1V8 in case of 1V8 IO DHCOR without the Empirion DCDC converter.
The 2V9 mode in case of AV96 DHCOR variant is used to reduce unnecessarily
high input voltage to the Empirion DCDC converter, so move it into matching
DTSI to stop confusing users.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
The stm32 ipcc mailbox driver supports only two interrupts (rx and tx), so
remove the unsupported "wakeup" one.
Note that the EXTI interrupt 61 has two roles : it is hierarchically linked
to the GIC IPCC "rx" interrupt, and it acts as a wakeup source.
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
In rcar_gen2_regulator_quirk(), for_each_matching_node_and_match() will
automatically increase and decrease the refcount. However, we should
call of_node_get() for the new reference created in 'quirk->np'.
Besides, we also should call of_node_put() before the 'quirk' being
freed.
Signed-off-by: Liang He <windhl@126.com>
Link: https://lore.kernel.org/r/20220701121804.234223-1-windhl@126.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This adds an appropriate SFP node for Trust Architecture 2.1 devices.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
SoC changes omaps mostly for missing of_node_put() calls and cosmetic
Kconfig changes. These can be all merged when suitable, there is no urgent
need to merge this as fixes.
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Merge tag 'omap-for-v5.20/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/soc
SoC changes omaps for v5.20 merge window
SoC changes omaps mostly for missing of_node_put() calls and cosmetic
Kconfig changes. These can be all merged when suitable, there is no urgent
need to merge this as fixes.
* tag 'omap-for-v5.20/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Kconfig: Fix indentation
ARM: OMAP2+: Fix refcount leak in omap3xxx_prm_late_init
ARM: OMAP2+: pdata-quirks: Fix refcount leak bug
ARM: OMAP2+: display: Fix refcount leak bug
ARM: OMAP2+: Fix refcount leak in omapdss_init_of
Link: https://lore.kernel.org/r/pull-1656918583-2801@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The USBH composed of EHCI and OHCI controllers needs the PHY clock to be
initialized first, before enabling (gating) them. The reverse is also
required when going to suspend.
So, add USBPHY clock as 1st entry in both controllers, so the USBPHY PLL
gets enabled 1st upon controller init. Upon suspend/resume, this also makes
the clock to be disabled/re-enabled in the correct order.
This fixes some IRQ storm conditions seen when going to low-power, due to
PHY PLL being disabled before all clocks are cleanly gated.
Fixes: 949a0c0dec85 ("ARM: dts: stm32: add USB Host (USBH) support to stm32mp157c")
Fixes: db7be2cb87ae ("ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151")
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Delete the node fixed clock managed by secure world with SCMI.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
LSE clock is provided by SCMI.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
The peripheral clock of CEC is not LSE but CEC.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Fixes stm32mp15*-scmi DTS files introduced in [1] to also access PWR
regulators through SCMI service. This is needed since enabling secure
only access to RCC clock and reset controllers also enables secure
access only on PWR voltage regulators reg11, reg18 and usb33 hence
these must also be accessed through SCMI Voltage Domain protocol.
This change applies on commit [2] that already corrects issues from
commit [1].
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Link: [1] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-7-alexandre.torgue@foss.st.com
Link: [2] https://lore.kernel.org/linux-arm-kernel/20220613071920.5463-1-alexandre.torgue@foss.st.com
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Use generic name for reset controller of AT91 devices to comply with
DT specifications.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220610092414.1816571-2-claudiu.beznea@microchip.com
Fix the following compilation warning:
arch/arm/boot/dts/sama5d2.dtsi:371.29-382.6: Warning
(avoid_unnecessary_addr_size): /ahb/apb/ethernet@f8008000:
unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
also defined at arch/arm/boot/dts/at91-sama5d2_icp.dts:353.8-363.3
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220615080633.1881196-2-claudiu.beznea@microchip.com
Since the Qualcomm sdhci-msm device-tree binding has been converted
to yaml format, 'make dtbs_check' reports issues with
inconsistent 'sdhci@' convention used for specifying the
sdhci nodes. The generic mmc bindings expect 'mmc@' format
instead.
Fix the same.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
[bjorn: Extracted from combined arm64 patch]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220514215424.1007718-2-bhupesh.sharma@linaro.org
- ADC and SPI support for the RZ/G2UL Soc and the RZ/G2UL SMARC EVK
development board,
- Ethernet support for the RZ/V2M SoC and the RZV2MEVK2 development
board,
- Thermal, IOMMU, Universal Flash Storage, octal Cortex-A55, and full
serial support for the R-Car S4-8 SoC on the Spider development
board,
- RTC support for the RZN1D-DB board,
- Miscellaneous fixes and improvements.
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Merge tag 'renesas-arm-dt-for-v5.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.20
- ADC and SPI support for the RZ/G2UL Soc and the RZ/G2UL SMARC EVK
development board,
- Ethernet support for the RZ/V2M SoC and the RZV2MEVK2 development
board,
- Thermal, IOMMU, Universal Flash Storage, octal Cortex-A55, and full
serial support for the R-Car S4-8 SoC on the Spider development
board,
- RTC support for the RZN1D-DB board,
- Miscellaneous fixes and improvements.
* tag 'renesas-arm-dt-for-v5.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (27 commits)
ARM: dts: rza2mevb: Fix LED node names
arm64: dts: renesas: Fix thermal-sensors on single-zone sensors
arm64: dts: renesas: spider-cpu: Enable SCIF0 on second connector
arm64: dts: renesas: r8a779f0: Add SCIF nodes
arm64: dts: renesas: r8a779f0: Add HSCIF nodes
arm64: dts: renesas: r8a779f0: Add DMA properties to SCIF3
arm64: dts: renesas: Add missing space after remote-endpoint
arm64: dts: renesas: rzg2ul-smarc-som: Enable ADC on SMARC platform
arm64: dts: renesas: rzg2ul-smarc: Enable RSPI1 on carrier board
arm64: dts: renesas: r8a779f0: Add CPU core clocks
arm64: dts: renesas: r8a779f0: Add CPUIdle support
arm64: dts: renesas: r8a779f0: Add secondary CA55 CPU cores
arm64: dts: renesas: r8a779f0: Add L3 cache controller
arm64: dts: renesas: r8a779a0: Add CPU0 core clock
arm64: dts: renesas: r8a779a0: Update to R-Car Gen4 compatible values
ARM: dts: r9a06g032-rzn1d400-db: Enable rtc0
arm64: dts: renesas: rzg2l-smarc: Use proper bool operator
arm64: dts: renesas: r8a779f0: Add UFS node
arm64: dts: renesas: r8a779f0: Add iommus to DMAC nodes
arm64: dts: renesas: r8a779f0: Add IPMMU nodes
...
Link: https://lore.kernel.org/r/cover.1656069634.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
