56795 Commits

Author SHA1 Message Date
Arnd Bergmann
14ef357550 dts updates for ti81xx for v5.1 merge window
Two changes to add support for McGill University's IceBoard telescope
 ARM + FPGA instrumentation board. This board is used for several
 telescopes around the world, see the related device tree commit for
 some interesting links for more information.
 
 Note that these changes are based on the related ti81xx soc changes.
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Merge tag 'omap-for-v5.1/dt-ti-81xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt

dts updates for ti81xx for v5.1 merge window

Two changes to add support for McGill University's IceBoard telescope
ARM + FPGA instrumentation board. This board is used for several
telescopes around the world, see the related device tree commit for
some interesting links for more information.

Note that these changes are based on the related ti81xx soc changes.

* tag 'omap-for-v5.1/dt-ti-81xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: dts: Adds device tree file for McGill's IceBoard, based on TI AM3874
  ARM: dts: ti81xx: Add dts boilerplate for all GPIO and SPI peripherals

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-15 13:58:37 +01:00
Arnd Bergmann
e4354c1aaf SoC updates for ti81xx for v5.1 merge window
Two changes to add legacy hwmod data for gpio and spi peripherals on
 ti81xx. We have not yet updated ti81xx to probe devices with ti-sysc
 interconnect target module driver, so these changes are still needed
 to make devices usable for the related device tree changes.
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Merge tag 'omap-for-v5.1/soc-ti-81xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt

SoC updates for ti81xx for v5.1 merge window

Two changes to add legacy hwmod data for gpio and spi peripherals on
ti81xx. We have not yet updated ti81xx to probe devices with ti-sysc
interconnect target module driver, so these changes are still needed
to make devices usable for the related device tree changes.

* tag 'omap-for-v5.1/soc-ti-81xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: ti81xx: Add hwmod boilerplate for all GPIO and SPI peripherals
  ARM: ti81xx: Move I2C entries in omap_hwmod_81xx to maintain grouping

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-15 13:57:58 +01:00
Arnd Bergmann
d50ce40a5a Drop one non-existent component from powerdomain list.
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Merge tag 'v5.0-rockchip-dts32fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes

Drop one non-existent component from powerdomain list.

* tag 'v5.0-rockchip-dts32fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: remove qos_cif1 from rk3188 power-domain
2019-02-15 13:41:11 +01:00
Arnd Bergmann
2ed5c2e3f2 SoC fixes for omaps for v5.0-rc cycle
This series contains two SoC regression fixes and one uninitialized
 variable fix:
 
 - Fix inverted nirq pin handling for omap5 that started producing
   warnings with earlier GIC direction checks and took a while to
   understand and confirm. Basically there are two sys_nirq pins
   that are bypassing peripheral modules and inverted automatically
   by the SoC and need to be handled with a custom irq_set_type()
 
 - Recent ti-sysc changes caused a regression to the pwm-omap-dmtimer
   code where the device tree handling code for timer source clock
   gets confused. It looks like we can remove that code eventually,
   but for now we just drop a bogus pm_runtime_irq_safe() for the
   timers with the related quirks caused by pm_runtime_irq_safe(),
   and have the standard assigned-clocks and assigned-clock-parents
   deal with setting the source clock
 
 - Fix potentially uninitialized value for display init code if
   regmap_read() fails
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Merge tag 'omap-for-v5.0/fixes-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes

SoC fixes for omaps for v5.0-rc cycle

This series contains two SoC regression fixes and one uninitialized
variable fix:

- Fix inverted nirq pin handling for omap5 that started producing
  warnings with earlier GIC direction checks and took a while to
  understand and confirm. Basically there are two sys_nirq pins
  that are bypassing peripheral modules and inverted automatically
  by the SoC and need to be handled with a custom irq_set_type()

- Recent ti-sysc changes caused a regression to the pwm-omap-dmtimer
  code where the device tree handling code for timer source clock
  gets confused. It looks like we can remove that code eventually,
  but for now we just drop a bogus pm_runtime_irq_safe() for the
  timers with the related quirks caused by pm_runtime_irq_safe(),
  and have the standard assigned-clocks and assigned-clock-parents
  deal with setting the source clock

- Fix potentially uninitialized value for display init code if
  regmap_read() fails

* tag 'omap-for-v5.0/fixes-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: Variable "reg" in function omap4_dsi_mux_pads() could be uninitialized
  ARM: dts: Configure clock parent for pwm vibra
  bus: ti-sysc: Fix timer handling with drop pm_runtime_irq_safe()
  ARM: OMAP5+: Fix inverted nirq pin interrupts with irq_set_type
  clocksource: timer-ti-dm: Fix pwm dmtimer usage of fck reparenting
2019-02-15 13:38:20 +01:00
Wolfram Sang
bceb26bffe at24 updates for v5.1
- finally remove legacy platform data as all users have been switched
   to using device properties and nvmem notifier chain
 - add support for the 'num-addresses' property
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Merge tag 'at24-5.1-updates-for-wolfram' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into i2c/for-5.1

at24 updates for v5.1

- finally remove legacy platform data as all users have been switched
  to using device properties and nvmem notifier chain
- add support for the 'num-addresses' property
2019-02-14 18:03:21 +01:00
Wolfram Sang
338618ad2a Merge branch 'i2c/for-current' into i2c/for-5.1 2019-02-14 17:46:56 +01:00
Bartosz Golaszewski
90733530a1 Merge branch 'v5.1/eeprom-for-bartosz' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into at24/for-next 2019-02-14 09:32:05 +01:00
Paolo Bonzini
08e16754ca KVM/ARM fixes for 5.0:
- Fix the way we reset vcpus, plugging the race that could happen on VHE
 - Fix potentially inconsistent group setting for private interrupts
 - Don't generate UNDEF when LORegion feature is present
 - Relax the restriction on using stage2 PUD huge mapping
 - Turn some spinlocks into raw_spinlocks to help RT compliance
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Merge tag 'kvm-arm-fixes-for-5.0' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into kvm-master

KVM/ARM fixes for 5.0:

- Fix the way we reset vcpus, plugging the race that could happen on VHE
- Fix potentially inconsistent group setting for private interrupts
- Don't generate UNDEF when LORegion feature is present
- Relax the restriction on using stage2 PUD huge mapping
- Turn some spinlocks into raw_spinlocks to help RT compliance
2019-02-13 19:39:24 +01:00
Christoph Hellwig
34e04eedd1 of: select OF_RESERVED_MEM automatically
The OF_RESERVED_MEM can be used if we have either CMA or the generic
declare coherent code built and we support the early flattened DT.

So don't bother making it a user visible options that is selected
by most configs that fit the above category, but just select it when
the requirements are met.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Rob Herring <robh@kernel.org>
2019-02-13 19:19:47 +01:00
Christoph Hellwig
dc2acded38 dma-mapping: add a kconfig symbol for arch_teardown_dma_ops availability
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Catalin Marinas <catalin.marinas@arm.com> # arm64
2019-02-13 19:12:50 +01:00
Christoph Hellwig
347cb6af87 dma-mapping: add a kconfig symbol for arch_setup_dma_ops availability
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Paul Burton <paul.burton@mips.com> # MIPS
Acked-by: Catalin Marinas <catalin.marinas@arm.com> # arm64
2019-02-13 19:12:33 +01:00
Linus Walleij
da4f07ddc1 ARM: dts: qcom-apq8060: Fix up interrupt parents
Before we fixed up the interrupt hierarchy for the SSBI
GPIO controller, we had to use the PM8058 directly to pick
interrupts. After making the interrupt controller work properly,
we can reference the real interrupt parent.

Signed-off-by: Brian Masney <masneyb@onstation.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-02-13 09:34:28 +01:00
Brian Masney
582648f5ef arm: dts: qcom: mdm9615: add interrupt controller properties
Add interrupt controller properties now that ssbi-gpio is a proper
hierarchical IRQ chip. The interrupts property is no longer needed so
remove it.

Note that the IRQs started at 24 instead of 192 like all of the other
PMICs. This is the same IRQs as the MPP for this board. qcom-pm8xxx.c
doesn't set the shared IRQs so this is highly likely to be a copy and
paste error.

Signed-off-by: Brian Masney <masneyb@onstation.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-02-13 09:33:55 +01:00
Brian Masney
a796fab2c6 arm: dts: qcom: msm8660: add interrupt controller properties
Add interrupt controller properties now that ssbi-gpio is a proper
hierarchical IRQ chip. The interrupts property is no longer needed so
remove it.

This change was tested on an APQ8060 DragonBoard.

Signed-off-by: Brian Masney <masneyb@onstation.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-02-13 09:33:12 +01:00
Brian Masney
e2f6c88812 arm: dts: qcom: apq8064: add interrupt controller properties
Add interrupt controller properties now that ssbi-gpio is a proper
hierarchical IRQ chip. The interrupts property is no longer needed so
remove it.

This change was not tested on any hardware but the same change was
tested on an APQ8060 DragonBoard with no issues.

Signed-off-by: Brian Masney <masneyb@onstation.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-02-13 09:32:44 +01:00
Trent Piepho
27f7717e23 ARM: dts: imx7d: Add node for PCIe PHY
This adds the PHY as a new node. The PCI-e controller node gains a
phandle property that points to it.

There isn't yet any code in the kernel that uses this device's
registers, but it will be added for a PCIe PLL erratum workaround.

Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2019-02-12 19:17:34 +00:00
Andreas Kemnade
947b780259 ARM: dts: omap3-gta04: declare backlight in lcd node
The lcd display of the gta04 has a backlight but the backlight
was not referenced in the lcd node, so screen blanking did
not turn off the backlight. Fix that.

Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-02-12 10:52:25 -08:00
Martyn Welch
361df77976 ARM: dts: am335x: Add support for Bosch Guardian
The Bosch Guardian is a TI am335x based device.

It's hardware specifications are as follows:

 * 256 MB DDR3 memory
 * 512 MB NAND Flash
 * USB OTG
 * RS232
 * MicroSD external storage
 * LCD Display interface

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
[tony@atomide.com: updated to use #include]
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-02-12 10:44:54 -08:00
Robin Murphy
fc67e6f120 ARM: 8835/1: dma-mapping: Clear DMA ops on teardown
Installing the appropriate non-IOMMU DMA ops in arm_iommu_detch_device()
serves the case where IOMMU-aware drivers choose to control their own
mapping but still make DMA API calls, however it also affects the case
when the arch code itself tears down the mapping upon driver unbinding,
where the ops now get left in place and can inhibit arch_setup_dma_ops()
on subsequent re-probe attempts.

Fix the latter case by making sure that arch_teardown_dma_ops() cleans
up whenever the ops were automatically installed by its counterpart.

Reported-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Fixes: 1874619a7df4 "ARM: dma-mapping: Set proper DMA ops in arm_iommu_detach_device()"
Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-02-12 15:20:59 +00:00
Mathieu Desnoyers
0ac569bf6a ARM: 8834/1: Fix: kprobes: optimized kprobes illegal instruction
commit e46daee53bb5 ("ARM: 8806/1: kprobes: Fix false positive with
FORTIFY_SOURCE") introduced a regression in optimized kprobes. It
triggers "invalid instruction" oopses when using kprobes instrumentation
through lttng and perf. This commit was introduced in kernel v4.20, and
has been backported to stable kernels 4.19 and 4.14.

This crash was also reported by Hongzhi Song on the redhat bugzilla
where the patch was originally introduced.

Link: https://bugzilla.redhat.com/show_bug.cgi?id=1639397
Link: https://bugs.lttng.org/issues/1174
Link: https://lore.kernel.org/lkml/342740659.2887.1549307721609.JavaMail.zimbra@efficios.com

Fixes: e46daee53bb5 ("ARM: 8806/1: kprobes: Fix false positive with FORTIFY_SOURCE")
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Reported-by: Robert Berger <Robert.Berger@ReliableEmbeddedSystems.com>
Tested-by: Robert Berger <Robert.Berger@ReliableEmbeddedSystems.com>
Acked-by: Kees Cook <keescook@chromium.org>
Cc: Robert Berger <Robert.Berger@ReliableEmbeddedSystems.com>
Cc: Masami Hiramatsu <mhiramat@kernel.org>
Cc: William Cohen <wcohen@redhat.com>
Cc: Laura Abbott <labbott@redhat.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: <stable@vger.kernel.org> # v4.14+
Cc: linux-arm-kernel@lists.infradead.org
Cc: patches@armlinux.org.uk
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-02-12 15:20:58 +00:00
Nathan Chancellor
de9c0d49d8 ARM: 8833/1: Ensure that NEON code always compiles with Clang
While building arm32 allyesconfig, I ran into the following errors:

  arch/arm/lib/xor-neon.c:17:2: error: You should compile this file with
  '-mfloat-abi=softfp -mfpu=neon'

  In file included from lib/raid6/neon1.c:27:
  /home/nathan/cbl/prebuilt/lib/clang/8.0.0/include/arm_neon.h:28:2:
  error: "NEON support not enabled"

Building V=1 showed NEON_FLAGS getting passed along to Clang but
__ARM_NEON__ was not getting defined. Ultimately, it boils down to Clang
only defining __ARM_NEON__ when targeting armv7, rather than armv6k,
which is the '-march' value for allyesconfig.

>From lib/Basic/Targets/ARM.cpp in the Clang source:

  // This only gets set when Neon instructions are actually available, unlike
  // the VFP define, hence the soft float and arch check. This is subtly
  // different from gcc, we follow the intent which was that it should be set
  // when Neon instructions are actually available.
  if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) {
    Builder.defineMacro("__ARM_NEON", "1");
    Builder.defineMacro("__ARM_NEON__");
    // current AArch32 NEON implementations do not support double-precision
    // floating-point even when it is present in VFP.
    Builder.defineMacro("__ARM_NEON_FP",
                        "0x" + Twine::utohexstr(HW_FP & ~HW_FP_DP));
  }

Ard Biesheuvel recommended explicitly adding '-march=armv7-a' at the
beginning of the NEON_FLAGS definitions so that __ARM_NEON__ always gets
definined by Clang. This doesn't functionally change anything because
that code will only run where NEON is supported, which is implicitly
armv7.

Link: https://github.com/ClangBuiltLinux/linux/issues/287

Suggested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-02-12 15:20:09 +00:00
Sudeep Holla
1241c72b6d ARM: dts: zynq: replace gpio-key,wakeup with wakeup-source property
Most of the legacy "gpio-key,wakeup" boolean property is already
replaced with "wakeup-source". However few occurrences of old property
has popped up again, probably from the remnants in downstream trees.

Replace the legacy properties with the unified "wakeup-source"
property introduced in the commit 700a38b27eef ("Input: gpio_keys -
switch to using generic device properties")

Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-12 13:53:33 +01:00
Adam Ford
1c207f911f ARM: dts: imx: Add support for Logic PD i.MX6QD EVM
The EVM consists of a system on module (SOM) and baseboard, and LCD.
This patch adds a DTSI file for the SOM and baseboard separately,
then a wrapper to combine them and specify processor type and a
LCD information.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-12 17:17:11 +08:00
Anson Huang
ee9ec3ea79 ARM: dts: imx6qdl-sabresd: remove reg_sensors' regulator-always-on
Now that all sensors supplied by reg_sensors have supported
regulator control, reg_sensors does NOT need to be always ON,
remove "regulator-always-on" to save power.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-12 17:17:11 +08:00
Anson Huang
14cc68e143 ARM: dts: imx6qdl-sabresd: add regulators control for mma8451 sensor
The mma8451 sensor driver has supported regulators control,
assign the power supplies for mma8451 to enable the control.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-12 17:17:11 +08:00
Anson Huang
72af502f17 ARM: dts: imx6qdl-sabresd: add regulators control for mag3110 sensor
The mag3110 sensor driver has supported regulators control,
assign the power supplies for mag3110 to enable the control.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-12 17:17:11 +08:00
Anson Huang
1e797150e0 ARM: dts: imx6qdl-sabresd: add regulator control for isl29023 sensor
The isl29023 light sensor driver has supported regulator control,
assign the power supply for isl29023 to enable the control.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-12 17:17:11 +08:00
Andrew Lunn
4a2c25961a ARM: dts: vf610: Add ZII SSMB DTU board
Add the Zodiac Digital Tapping Unit, a VF610 based network device with
5 Ethernet ports. One of these ports supports 1000Base-T2.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-12 17:17:10 +08:00
Philipp Zabel
8de81c89d0 ARM: dts: pfla02: add ksz9031 clock skew values
The pfla02 SoM has a Micrel KSZ9031RNX ethernet phy connected to the FEC,
which needs RX and TX clock skew settings to compensate for differences
in line length. The skew values are taken from barebox commit
4c65c20f1071 ("ARM: pfla02: Set new ethernet phy tx timings"), which
is based on patches originally provided by Phytec:

    TX_CLK line is approx. 54mm longer than other TX lines which adds
    a delay of 0.36ns. RGMII need a delay of min. 1.0ns. This mean we
    have to add a delay of 0.64ns. We choose 0.78 to have a little gap.
    This can be done by setting GTX pad skew value to 11100
    Also add a delay for the RX delay lines, needed for the Duallite
    variant.  => Set register 2.8 (RGMII Clock Pad Skew) to 0x039F.

Cc: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-12 17:17:10 +08:00
Marco Felsch
bffe0d85e5 ARM: dts: imx6qdl-phytec-pfla02: add missing interrupt-controller property
The DA9063 device need the required "interrupt-controller" property as
documented by the bindings [1].

[1] Documentation/devicetree/bindings/mfd/da9063.txt

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-12 17:17:10 +08:00
Bartosz Golaszewski
339850f23a ARM: davinci: da830-evm: remove legacy usb helpers
The logic implemented by these routines now lives in the da8xx-ohci
driver. Remove dead code.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-02-12 13:48:59 +05:30
Bartosz Golaszewski
2435854e2a ARM: davinci: omapl138-hawk: remove legacy usb helpers
The logic implemented by these routines now lives in the da8xx-ohci
driver. Remove dead code.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-02-12 13:48:58 +05:30
Bartosz Golaszewski
1703cf5d4f ARM: davinci: da830-evm: use gpio lookup entries for usb gpios
Add lookup entries for vbus and overcurrent gpios for da830-evm.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-02-12 13:28:41 +05:30
Bartosz Golaszewski
c08df69149 ARM: davinci: omapl138-hawk: use gpio lookup entries for usb gpios
Add lookup entries for the vbus and overcurrent gpios for omapl138-hawk.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-02-12 13:28:41 +05:30
Martin Blumenstingl
99f0619b0d ARM: dts: meson8b: ec100: add the GPIO line names
This adds the GPIO line names from the schematics to get them displayed
in the debugfs output of each GPIO controller.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-11 12:52:26 -08:00
Martin Blumenstingl
3e7db1c1b7 ARM: dts: meson8b: ec100: improve the description of the regulators
USB_VBUS is a controlled by a Silergy SY6288CCAC-GP 2A Power
Distribution Switch. The name of it's enable GPIO signal is USB_PWR_EN.

VCC5V is supplied by the main power input called PWR_5V_STB. The name of
it's enable GPIO signal is 3V3_5V_EN.

VCC3V3, VCC_DDR3_1V5 and VCCK (the CPU power supply) each use a separate
Silergy SY8089AAC-GP 2A step down regulator. They are all supplied by the
board's main 5V. VCC3V3 and VCC_DDR3_1V5 are fixed regulators while the
voltage of VCCK can be changed by changing it's feedback voltage via
PWM_C.

VCC1V8 is an ABLIC S-1339D18-M5001-GP fixed voltage regulator which is
supplied by VCC3V3.

VCC_RTC is a Global Mixed-mode Technology Inc. G918T12U-GP LDO which. It
is supplied by either VCC3V3 (when the board is powered) or the RTC coin
cell battery.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-11 12:52:26 -08:00
Martin Blumenstingl
b7d10841e5 ARM: dts: meson8b: ec100: enable the Ethernet PHY interrupt
The INTR32 pin of the IP101GR Ethernet PHY is routed to the GPIOH_3 pad
on the SoC.
Enable the interrupt function of the PHY's INTR32 pin to switch it from
it's default "receive error" mode to "interrupt pin" mode.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-11 12:52:26 -08:00
Martin Blumenstingl
e7e871b50f ARM: dts: meson8m2: mxiii-plus: add iio-hwmon for the chip temperature
SAR ADC enabled channel 8 can be used to measure the chip temperature.
This can be made available to the hwmon subsystem by using iio-hwmon.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-11 12:52:26 -08:00
Martin Blumenstingl
a6c9492826 ARM: dts: meson8b: odroidc1: add iio-hwmon for the chip temperature
SAR ADC enabled channel 8 can be used to measure the chip temperature.
This can be made available to the hwmon subsystem by using iio-hwmon.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-11 12:52:26 -08:00
Martin Blumenstingl
1a4f28ab25 ARM: dts: meson8b: ec100: add iio-hwmon for the chip temperature
SAR ADC enabled channel 8 can be used to measure the chip temperature.
This can be made available to the hwmon subsystem by using iio-hwmon.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-11 12:52:26 -08:00
Martin Blumenstingl
bbbcf64360 ARM: dts: meson8b: add the temperature calibration data for the SAR ADC
The SAR ADC can measure the chip temperature of the SoC. This only
works if the chip is calibrated and if the calibration data is written
to the correct registers. The calibration data is stored in the upper
two bytes of eFuse offset 0x1f4.

This adds the eFuse cell for the temperature calibration data and
passes it to the SAR ADC. We also need to pass the HHI sysctrl node to
the SAR ADC because the 4th TSC (temperature sensor calibration
coefficient) bit is stored in the HHI region (unlike bits [3:0] which
are stored directly inside the SAR ADC's register area).

On boards that have the SAR ADC enabled channel 8 can be used to
measure the chip temperature.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-11 12:52:26 -08:00
Martin Blumenstingl
f4c6e8e223 ARM: dts: meson8: add the temperature calibration data for the SAR ADC
The SAR ADC can measure the chip temperature of the SoC. This only
works if the chip is calibrated and if the calibration data is written
to the correct registers. The calibration data is stored in the upper
two bytes of eFuse offset 0x1f4.

This adds the eFuse cell for the temperature calibration data and
passes it to the SAR ADC. We also need to pass the HHI sysctrl node to
the SAR ADC because the 4th TSC (temperature sensor calibration
coefficient) bit is stored in the HHI region (unlike bits [3:0] which
are stored directly inside the SAR ADC's register area).

On boards that have the SAR ADC enabled channel 8 can be used to
measure the chip temperature.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-11 12:52:26 -08:00
Martin Blumenstingl
c0ad99a2de ARM: dts: meson8m2: use the Meson8m2 specific SAR ADC compatible
The SAR ADC on Meson8m2 is slightly different compared to Meson8. The
ADC functionality is identical but the calibration of the internal
thermal sensor is different.

Use the Meson8m2 specific compatible so the temperature sensor is
calibrated correctly on boards using the Meson8m2 SoC.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-11 12:52:25 -08:00
Martin Blumenstingl
b6db3936f2 ARM: dts: meson: switch the clock controller to the HHI register area
The clock controller on Meson8/Meson8m2 and Meson8b is part of a
register region called "HHI". This register area contains more
functionality than just a clock controller:
- the clock controller
- some reset controller bits
- temperature sensor calibration data (on Meson8b and Meson8m2 only)
- HDMI controller

Allow access to this HHI register area as "system controller". Also
migrate the Meson8 and Meson8b clock controllers to this new node.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-11 12:52:25 -08:00
Martin Blumenstingl
29f0023d01 ARM: dts: meson8b: fix the Ethernet data line signals in eth_rgmii_pins
According to the Odroid-C1+ schematics the Ethernet TXD1 signal is
routed to GPIOH_5 and the TXD0 signal is routed to GPIOH_6.
The public S805 datasheet shows that TXD0 can be routed to DIF_2_P and
TXD1 can be routed to DIF_2_N instead.

The pin groups eth_txd0_0 (GPIOH_6) and eth_txd0_1 (DIF_2_P) are both
configured as Ethernet TXD0 and TXD1 data lines in meson8b.dtsi. At the
same time eth_txd1_0 (GPIOH_5) and eth_txd1_1 (DIF_2_N) are configured
as TXD0 and TXD1 data lines as well.
This results in a bad Ethernet receive performance. Presumably this is
due to the eth_txd0 and eth_txd1 signal being routed to the wrong pins.
As a result of that data can only be transmitted on eth_txd2 and
eth_txd3. However, I have no scope to fully confirm this assumption.

The vendor u-boot sources for Odroid-C1 use the following Ethernet
pinmux configuration:
  SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, 0x3f4f);
  SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_7, 0xf00000);
This translates to the following pin groups in the mainline kernel:
- register 6 bit  0: eth_rxd1 (DIF_0_P)
- register 6 bit  1: eth_rxd0 (DIF_0_N)
- register 6 bit  2: eth_rx_dv (DIF_1_P)
- register 6 bit  3: eth_rx_clk (DIF_1_N)
- register 6 bit  6: eth_tx_en (DIF_3_P)
- register 6 bit  8: eth_ref_clk (DIF_3_N)
- register 6 bit  9: eth_mdc (DIF_4_P)
- register 6 bit 10: eth_mdio_en (DIF_4_N)
- register 6 bit 11: eth_tx_clk (GPIOH_9)
- register 6 bit 12: eth_txd2 (GPIOH_8)
- register 6 bit 13: eth_txd3 (GPIOH_7)
- register 7 bit 20: eth_txd0_0 (GPIOH_6)
- register 7 bit 21: eth_txd1_0 (GPIOH_5)
- register 7 bit 22: eth_rxd3 (DIF_2_P)
- register 7 bit 23: eth_rxd2 (DIF_2_N)

Drop the eth_txd0_1 and eth_txd1_1 groups from eth_rgmii_pins to fix the
Ethernet transmit performance on Odroid-C1. Also add the eth_rxd2 and
eth_rxd3 groups so we don't rely on the bootloader to set them up.

iperf3 statistics before this change:
- transmitting from Odroid-C1: 741 Mbits/sec (0 retries)
- receiving on Odroid-C1: 199 Mbits/sec (1713 retries)

iperf3 statistics after this change:
- transmitting from Odroid-C1: 667 Mbits/sec (0 retries)
- receiving on Odroid-C1: 750 Mbits/sec (0 retries)

Fixes: b96446541d8390 ("ARM: dts: meson8b: extend ethernet controller description")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: Emiliano Ingrassia <ingrassia@epigenesys.com>
Cc: Linus Lüssing <linus.luessing@c0d3.blue>
Tested-by: Emiliano Ingrassia <ingrassia@epigenesys.com>
Reviewed-by: Emiliano Ingrassia <ingrassia@epigenesys.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-02-11 12:52:25 -08:00
Philippe Schenker
a822029a0c ARM: dts: Add stmpe-adc DT node to Toradex iMX6 modules
Add the stmpe-adc DT node as found on Toradex iMX6 modules

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-11 09:22:27 +08:00
Manivannan Sadhasivam
da8782f673 ARM: dts: Add devicetree compatibles for LS1021A based boards
Add missing devicetree compatibles for the following LS1021A based
boards:

ls1021a-moxa-uc-8410a.dts
ls1021a-qds.dts
ls1021a-twr.dts

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-11 09:22:27 +08:00
Stefan Agner
063182a4c8 ARM: dts: colibri: use valid range configuration for weim
A valid WEIM range configuration must specify range entries for
all four chip selects. This fixes an error on boot:
  imx-weim: probe of 21b8000.weim failed with error -22

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-11 09:22:26 +08:00
Martyn Welch
82ae9038dd ARM: dts: imx6: Add support for Phytec phyBOARD i.MX6UL Segin
The Phytec phyBOARD Segin is i.MX6 based SBC, available with either an
i.MX6UL or i.MX6ULL SOM and various add-on boards.

The following adds support for the "Full Featured" version of the Segin,
which is provided with the i.MX6UL SOM and the PEB-EVAL-01 evaluation
module.

Its hardware specifications are:

 * 512MB DDR3 memory
 * 512MB NAND flash
 * Dual 10/100 Ethernet
 * USB Host and USB OTG
 * RS232
 * MicroSD external storage
 * Audio, RS232, I2C, SPI, CAN headers
 * Further I/O options via A/V and Expansion headers

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-11 09:22:26 +08:00
Stefan Agner
d2b91ab148 ARM: dts: imx6*-apalis/-colibri: mark I2C recovery GPIOs as open drain
Since commit d2d0ad2aec4a ("i2c: imx: use open drain for recovery
GPIO") GPIO lib expects this GPIO to be configured as open drain.
Make sure we define this GPIO as open drain in the device tree.
This gets rid of the following warning:
  gpio-81 (scl): enforced open drain please flag it properly in DT/ACPI DSDT/board file

Note that currently the i.MX pinctrl driver does not support
enabling open drain directly, so this patch has no effect in
practice. Open drain is enabled by the fixed pinmux entry.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Philippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-02-11 09:22:26 +08:00