2366 Commits

Author SHA1 Message Date
Abel Vesa
2daa9555ba phy: qcom-qmp-usb: Add Qualcomm X1E80100 USB3 PHY support
The X1E80100 platform has two instances of the USB3 UNI phy attached
to the multi-port USB controller, add definition for these.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20231122-phy-qualcomm-usb3-uniphy-x1e80100-v3-2-273814c300f8@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-12-21 22:40:00 +05:30
Abel Vesa
d7b3579f84 phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys
The X1E80100 has three copies of an USB/DP compbo PHY, add support for this
to the Qualcomm QMP PHY driver.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20231201-x1e80100-phy-combo-v1-2-6938ec41f3ac@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-12-21 22:39:59 +05:30
Chunfeng Yun
9b27303003 phy: mediatek: tphy: add support force phy mode switch
this is used to be compatible with old SoCs, such as mt8195, which shares
t-phy between usb3 and pcie controller, usually, it's default mode is pcie
rc mode, and could use force mode to switch into usb3 mode, because pericfg
layer doesn't provide mode switch, also no efuse or jumper can be used;
Currently, only support switch from default pcie mode to usb3;
Note: don't use this way on new SoCs, use pericfg layer's mode switch
instead (by perperty "mediatek,syscon-type").

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lore.kernel.org/r/20231211025624.28991-2-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-12-21 22:39:59 +05:30
Wang Jinchao
57f31e911e phy: phy-can-transceiver: insert space after include
Maintain Consistent Formatting: Insert Space after #include

Signed-off-by: Wang Jinchao <wangjinchao@xfusion.com>
Reviewed-by: Marc Kleine-Budde <mkl@pengutronix.de>
Link: https://lore.kernel.org/r/202312151407+0800-wangjinchao@xfusion.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-12-21 22:39:59 +05:30
Can Guo
5301b7a040 phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY Settings
The registers, which are being touched in current SM8550 UFS PHY settings,
and the values being programmed are mainly the ones working for HS-G4 mode,
meanwhile, there are also a few ones somehow taken from HS-G5 PHY settings.
However, even consider HS-G4 mode only, some of them are incorrect and some
are missing. Rectify the HS-G4 PHY settings by strictly aligning with the
SM8550 UFS PHY Hardware Programming Guide suggested HS-G4 PHY settings.

Fixes: 1679bfef906f ("phy: qcom-qmp-ufs: Add SM8550 support")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Can Guo <quic_cang@quicinc.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Link: https://lore.kernel.org/r/1701520577-31163-10-git-send-email-quic_cang@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-12-21 22:39:44 +05:30
Randy Dunlap
54c899f0d6 phy: renesas: phy-rcar-gen2: use select for GENERIC_PHY
Change the last "depends on GENERIC_PHY" to use select, like the
other 170+ Kconfig users do. This can help prevent circular
dependency issues.

Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Kishon Vijay Abraham I <kishon@kernel.org>
Cc: linux-phy@lists.infradead.org
Link: https://lore.kernel.org/r/20231204234917.23509-1-rdunlap@infradead.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-12-21 22:39:34 +05:30
Abel Vesa
ee6fcc0f33 phy: qcom-qmp: qserdes-txrx: Add v7 register offsets
The X1E80100 platform bumps the HW version of QMP phy to v7 for USB and PCIE.
Add the new qserdes TX RX offsets in a dedicated header file.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-7-dfd1c375ef61@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-12-21 22:37:39 +05:30
Abel Vesa
762c3565f3 phy: qcom-qmp: qserdes-txrx: Add V6 N4 register offsets
There is a variant of V6 offsets that are different, the QMP PHY N4,
and it is found on the X1E80100 platform.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-6-dfd1c375ef61@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-12-21 22:37:39 +05:30
Abel Vesa
bc546cc85c phy: qcom-qmp: qserdes-com: Add v7 register offsets
The X1E80100 platform bumps the HW version of QMP phy to v7 for USB
and PCIE g3x2. Add the new qserdes com offsets in a dedicated
header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-5-dfd1c375ef61@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-12-21 22:37:39 +05:30
Abel Vesa
8d4f9f8010 phy: qcom-qmp: pcs-usb: Add v7 register offsets
The X1E80100 platform bumps the HW version of QMP phy to v7 for USB.
Add the new PCS USB specific offsets in a dedicated header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-4-dfd1c375ef61@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-12-21 22:37:39 +05:30
Abel Vesa
7b98cf0e9b phy: qcom-qmp: pcs: Add v7 register offsets
The X1E80100 platform bumps the HW version of QMP phy to v7 for USB,
and PCIe. Add the new PCS offsets in a dedicated header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-3-dfd1c375ef61@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-12-21 22:37:39 +05:30
Abel Vesa
a40542507b phy: qcom-qmp: qserdes-txrx: Add some more v6.20 register offsets
Add some missing v6.20 registers offsets that are needed by the new
Snapdragon X Elite (X1E80100) platform.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-2-dfd1c375ef61@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-12-21 22:37:39 +05:30
Abel Vesa
2226ec072e phy: qcom-qmp: qserdes-com: Add some more v6 register offsets
Add some missing V6 registers offsets that are needed by the new
Snapdragon X Elite (X1E80100) platform.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-1-dfd1c375ef61@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-12-21 22:37:39 +05:30
Rohit Agarwal
7f6f9e0def phy: qcom-qmp-usb: Add Qualcomm SDX75 USB3 PHY support
Add support for USB3 QMP PHY found in SDX75 platform.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20231117061501.537529-1-quic_rohiagar@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-11-27 18:40:07 +05:30
Alex Bee
62ff41017e phy: phy-rockchip-inno-usb2: Add RK3128 support
Add registers to support the 2-port usb2 phy found in RK312x SoC familiy.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20231119121340.109025-3-knaerzche@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-11-27 18:36:29 +05:30
Alex Bee
2fda590994 phy: rockchip-inno-usb2: Split ID interrupt phy registers
Commit 51a9b2c03dd3 ("phy: rockchip-inno-usb2: Handle ID IRQ") added ID
detection interrupt registers. However the current implementation assumes
that falling and rising edge interrupt are always enabled in registers
spanning over subsequent bits.
That is not the case for RK3128's version of the phy and this
implementation can't be used as-is, since there are bits with different
purpose in between.

This splits up the register definitions for id_det_en, id_det_en and
id_det_clr registers in rising and falling edge variants.
It's required as preparation to support RK3128's Innosilicon usb2 phy as
well in this driver and matches pretty much to what the vendor does, so I'm
not expecting issues for other SoCs with that change.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20231119121340.109025-2-knaerzche@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-11-27 18:36:29 +05:30
Christophe JAILLET
772dd70a5e phy: core: Remove usage of the deprecated ida_simple_xx() API
ida_alloc() and ida_free() should be preferred to the deprecated
ida_simple_get() and ida_simple_remove().

This is less verbose.

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/d2323636c6cd2ec22f73a0ae6c2d34ac99b4abd5.1698854255.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-11-16 17:03:51 +05:30
Neil Armstrong
80c1afe8c5 phy: qcom: qmp-combo: add QMP USB3/DP PHY tables for SM8650
Add QMP USB3/DP Combo PHY support for the SM8650 platform.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-phy-v2-7-a543a4c4b491@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-11-16 17:01:02 +05:30
Neil Armstrong
c954b6d347 phy: qcom: qmp-pcie: add QMP PCIe PHY tables for SM8650
Add QMP PCIe PHY support for the SM8650 platform.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-phy-v2-6-a543a4c4b491@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-11-16 17:01:02 +05:30
Neil Armstrong
7c4bf8cb9d phy: qcom: qmp-ufs: add QMP UFS PHY tables for SM8650
Add QMP UFS PHY support for the SM8650 platform.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-phy-v2-5-a543a4c4b491@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-11-16 17:01:02 +05:30
Linus Torvalds
bfafa2c19d phy-for-6.6
- New Support
   - Qualcomm sa8775p qmp-pcie support, IPQ5018 support,
     SC7280 qmp-ufs support
  - Mediatek MT8188 support
 
 - Updates
   - Device tree device_get_match_data() usage and dropping
     of_match_device() calls
   - Qualcomm qmp usb and combo phy updates for v6 register layout
   - Qualcomm eusb2-repeater updates for tuning overrides, regmap fields
   - STih407 usb binding and ralink usb-phy yaml conversion
   - renesas r8a779f0 serdes init sequencing updates
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEE+vs47OPLdNbVcHzyfBQHDyUjg0cFAmVE5rcACgkQfBQHDyUj
 g0dadhAAhdFR/vj17+Ah7Ru8AShPy1tNLMyFss6+X1+wUBmUYbc5gAmusMi0lIyQ
 n0GofAVARuNOYK+kNocOWeAqA8w9urKkCtfkAl29KzJ06YqZ0XVpOIW+z+GDCCiy
 ekGvgSwKpns/g8eZGRQ2r4O5tdwKolkVSk0SgLeeqtUfGKxLx6U+LS9/XOeO6GlZ
 XQaUpohuutr7xln8JTsJNWIOmYvqWZHUNe5R1Mdy15gyRYOLPZMqaSMPXhiUd/iL
 BJGHtWFJfqQRr7hbma6Ri9DunZAAGTdyfAefdVitTt66Ls9lT/jHxm8ky19C7oTC
 8GgfCMdE1ZdgxckGRKDWUBXIGT61x7dJ4EDfOQo25RRTOEh/1JPFOFvsWICTXHkt
 xLBnip8zX7f5OgejAGQXlXjsrmpBaYZM8J6+02oc9AzA2FCiD/ca7oB420Q5v9uw
 LMuLdv6eOHrzCEwhYOJYR4t4XxRCDFKk5QTu9LQWasUB5fJMJzZ8118s+2AylBEw
 l7EX6XFJ7nlCVUGiFHnqJCPwZDnnJw+irvre8Id0QYoJxW6XsSET49Us5Uh9I0vs
 grhn0WNVJ93yk87u2uTJkfhXUjajy6Mw0oy/zLyZ3KztY4u5dx/8NV+pYNEiGFiO
 ggc63Mv/QdR9KbJiKsJtxTOyuw1eG0e2j3RrEQvxqaBEPZLvTjs=
 =y7oj
 -----END PGP SIGNATURE-----

Merge tag 'phy-for-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

Pull generic phy updates from Vinod Koul:
 "New Support:
   - Qualcomm sa8775p qmp-pcie, IPQ5018, and SC7280 qmp-ufs support
   - Mediatek MT8188 support

  Updates:
   - Device tree device_get_match_data() usage and dropping
     of_match_device() calls
   - Qualcomm qmp usb and combo phy updates for v6 register layout
   - Qualcomm eusb2-repeater updates for tuning overrides, regmap fields
   - STih407 usb binding and ralink usb-phy yaml conversion
   - renesas r8a779f0 serdes init sequencing updates"

* tag 'phy-for-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (32 commits)
  phy: Remove duplicated include in phy-ralink-usb.c
  phy: Kconfig: Select GENERIC_PHY for GENERIC_PHY_MIPI_DPHY
  phy: qcom-qmp-pcie: add endpoint support for sa8775p
  dt-bindings: phy: ralink-usb-phy: convert to dtschema
  dt-bindings: phy: Convert PXA1928 USB/HSIC PHY to DT schema
  phy: Drop unnecessary of_match_device() calls
  phy: rockchip-inno-usb2: Drop unnecessary DT includes
  phy: Use device_get_match_data()
  phy: realtek: Replace of_device.h with explicit includes
  phy: renesas: r8a779f0-ether-serdes: Add .exit() ops
  phy: renesas: r8a779f0-ether-serdes: Reset in .init()
  phy: qcom-qmp-combo: use v6 registers in v6 regs layout
  phy: qcom-qmp-usb: move PCS v6 register to the proper header
  phy: qcom-qmp-combo: fix the prefix for the PCS_USB v6 registers
  phy: sun4i-usb: update array size
  phy: qualcomm: phy-qcom-eusb2-repeater: Add tuning overrides
  phy: qualcomm: phy-qcom-eusb2-repeater: Zero out untouched tuning regs
  phy: qualcomm: phy-qcom-eusb2-repeater: Use regmap_fields
  dt-bindings: phy: qcom,snps-eusb2-repeater: Add magic tuning overrides
  dt-bindings: phy: Add compatible for Mediatek MT8188
  ...
2023-11-03 19:06:12 -10:00
Yang Li
d688c8264b phy: Remove duplicated include in phy-ralink-usb.c
./drivers/phy/ralink/phy-ralink-usb.c: linux/platform_device.h is included more than once.

Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=6851
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Link: https://lore.kernel.org/r/20231017031635.105993-1-yang.lee@linux.alibaba.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-23 11:55:36 +05:30
Sakari Ailus
d0ec7b9c31 phy: Kconfig: Select GENERIC_PHY for GENERIC_PHY_MIPI_DPHY
GENERIC_PHY can be selected by GENERIC_PHY_MIPI_DPHY directly as
GENERIC_PHY has no dependencies. This way drivers that depend on
GENERIC_PHY_MIPI_DPHY can avoid having to select both --- which they
apparently often omit, too, which further leads to build failures.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
Tested-by: Randy Dunlap <rdunlap@infradead.org>
Link: https://lore.kernel.org/r/20231017080354.538047-1-sakari.ailus@linux.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-23 11:54:49 +05:30
Mrinmay Sarkar
8e11a94e15 phy: qcom-qmp-pcie: add endpoint support for sa8775p
Add support for dual lane end point mode PHY found on sa8755p platform.

Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/1697715430-30820-4-git-send-email-quic_msarkar@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-23 11:54:21 +05:30
Linus Torvalds
fe3cfe869d phy fixes for 6.6
- Driver fixes for
    - mapphone-mdm6600 runtime pm & pinctrl handling fixes
    - Qualcomm qmp usb pcs register fixes, qmp pcie register size warning
      fix, m31 fixes for wrong pointer in PTR_ERR and dropping wrong vreg
      check, qmp combo fix for 8550 power config register
    - realtek usb fix for debugfs_create_dir() and kconfig dependency
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEE+vs47OPLdNbVcHzyfBQHDyUjg0cFAmU1VYIACgkQfBQHDyUj
 g0fhAw/+I2F51l+SJ5Y2UKnr4BE2aaVjd1CisnoGKFZ2QCMt76mWHRaZZ1YEYAYR
 NK77rBuR80LXUj9mMoHVdIWleH/tlvDJ8LFpA9H+fvDoKkjjK4g66fCG9GU0V3qv
 oWerSiwaAVGb/yLokJ4KwEaumcMukCsGf6P3SWk/XeFwaxySixcD4nwFzpAalX0z
 ZXot62Xq1cLEriH6yJslU3iySWGfpAL12ygYOFVuaW02tUEmIH+zM7L4jNDgldHD
 gr45T8wbh5M2r8uE9x7thMafk7mcKEjiyV5Er2SLgTwh9fRXa3gOw1I+NHcGM8sM
 YnIXlB+hDZ4SuJKWDxsQn+Y3N/+byvHrYMiKvuN32ysZRA8aIvkqdUMPJyZBYk3j
 ecp4TH8YJ3iEVVDbUsv5v/uBH/drlBdJNLEdc71RiJfppsxI+97okdOGXQBT04Lu
 alifV/ehLaZamJrVzpD1wFlYaZnAc0DnwqxZlepOMghzfiA7qQgV70wlMAkL81DX
 R4da2kgmVWlXcjEmOfDUSFsEaLHiZ9ArZabru0kdq1TYOt8/oVnl9t9T/qqB6qs3
 JioLTLXUry5hFpaGjuGTJeRhkJRnOjSAYuCLiyJGd0tcgA05dHXNHOwIIrJTVi4K
 ksz/x2G+lwQP8EnKpctEkY4v5KKGmJPspymzHTXsAcUFdZr7F4w=
 =ugiS
 -----END PGP SIGNATURE-----

Merge tag 'phy-fixes-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

Pull phy fixes from Vinod Koul:

 - mapphone-mdm6600 runtime pm & pinctrl handling fixes

 - Qualcomm qmp usb pcs register fixes, qmp pcie register size warning
   fix, m31 fixes for wrong pointer in PTR_ERR and dropping wrong vreg
   check, qmp combo fix for 8550 power config register

 - realtek usb fix for debugfs_create_dir() and kconfig dependency

* tag 'phy-fixes-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy:
  phy: realtek: Realtek PHYs should depend on ARCH_REALTEK
  phy: qualcomm: Fix typos in comments
  phy: qcom-qmp-combo: initialize PCS_USB registers
  phy: qcom-qmp-combo: Square out 8550 POWER_STATE_CONFIG1
  phy: qcom: m31: Remove unwanted qphy->vreg is NULL check
  phy: realtek: usb: Drop unnecessary error check for debugfs_create_dir()
  phy: qcom: phy-qcom-m31: change m31_ipq5332_regs to static
  phy: qcom: phy-qcom-m31: fix wrong pointer pass to PTR_ERR()
  dt-bindings: phy: qcom,ipq8074-qmp-pcie: fix warning regarding reg size
  phy: qcom-qmp-usb: split PCS_USB init table for sc8280xp and sa8775p
  phy: qcom-qmp-usb: initialize PCS_USB registers
  phy: mapphone-mdm6600: Fix pinctrl_pm handling for sleep pins
  phy: mapphone-mdm6600: Fix runtime PM for remove
  phy: mapphone-mdm6600: Fix runtime disable on probe
2023-10-22 07:11:10 -10:00
Rob Herring
dd69a6379a phy: Drop unnecessary of_match_device() calls
If probe is reached, we've already matched the device and in the case of
DT matching, the struct device_node pointer will be set. Therefore, there
is no need to call of_match_device() in probe.

Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20231009172923.2457844-16-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-13 15:47:53 +05:30
Rob Herring
8b6fba3e79 phy: rockchip-inno-usb2: Drop unnecessary DT includes
Neither of_address.h or of_platform.h are used in the driver, so drop them.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20231009172923.2457844-17-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-13 15:46:09 +05:30
Rob Herring
21bf6fc47a phy: Use device_get_match_data()
Use preferred device_get_match_data() instead of of_match_device() to
get the driver match data. With this, adjust the includes to explicitly
include the correct headers.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20231009172923.2457844-15-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-13 15:45:40 +05:30
Rob Herring
7e909370a5 phy: realtek: Replace of_device.h with explicit includes
The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other and pull in various other headers. In
preparation to fix this, adjust the includes for what is actually needed.

of_device.h isn't needed, but platform_device.h was implicitly included by
it.

Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20231010205701.1585026-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-13 15:43:59 +05:30
Yoshihiro Shimoda
1a5361189b phy: renesas: r8a779f0-ether-serdes: Add .exit() ops
Add r8a779f0_eth_serdes_exit() to clear the initialized flag
for re-initializing this PHY if needed.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20231011081817.257113-3-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-13 15:43:30 +05:30
Yoshihiro Shimoda
aa4c0bbf82 phy: renesas: r8a779f0-ether-serdes: Reset in .init()
Reset this PHY in .init() instead of probe() for re-initializing
this PHY after probed correctly.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20231011081817.257113-2-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-13 15:43:30 +05:30
Dmitry Baryshkov
b5ec2824d7 phy: qcom-qmp-combo: use v6 registers in v6 regs layout
Make sure that we use only v6 registers in qmp_v6_usb3phy_regs_layout.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230928105445.1210861-4-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-13 15:35:21 +05:30
Dmitry Baryshkov
5077b136fd phy: qcom-qmp-usb: move PCS v6 register to the proper header
The commit 39bbf82d8c2b ("phy: qcom-qmp: pcs-usb: Add v6 register
offsets") incorrectly added plain PCS registers to the PCS_USB header.
Move them to a proper location.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230928105445.1210861-3-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-13 15:35:16 +05:30
Dmitry Baryshkov
579483ecd8 phy: qcom-qmp-combo: fix the prefix for the PCS_USB v6 registers
For all other generations, we have been using just the QPHY prefix for
the PCS registers. Remove the _USB part of the QPHY_USB prefix.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230928105445.1210861-2-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-13 15:35:09 +05:30
Christophe JAILLET
9e34abc7ab phy: sun4i-usb: update array size
With gcc 12.3.0, when this file is built, we get errors such as:

drivers/phy/allwinner/phy-sun4i-usb.c: In function ‘sun4i_usb_phy_probe’:
drivers/phy/allwinner/phy-sun4i-usb.c:790:52: error: ‘_vbus’ directive output may be truncated writing 5 bytes into a region of size between 2 and 12 [-Werror=format-truncation=]
  790 |                 snprintf(name, sizeof(name), "usb%d_vbus", i);
      |                                                    ^~~~~
drivers/phy/allwinner/phy-sun4i-usb.c:790:17: note: ‘snprintf’ output between 10 and 20 bytes into a destination of size 16
  790 |                 snprintf(name, sizeof(name), "usb%d_vbus", i);
      |                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Because of the possible value of 'i', this can't be an issue in real world
application, but in order to have "make W=1" work correctly, give more
space for 'name'.

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/0bc81612171baaa6d5dff58c8e009debc03e1ba8.1693735840.git.christophe.jaillet@wanadoo.fr
[vkoul: updated patch title]
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-13 15:34:39 +05:30
Vinod Koul
9bcf876119 Merge branch 'fixes' into next
Merge fixes into next as qmp phy patches on list depend on it
2023-10-13 15:29:08 +05:30
Vladimir Oltean
139ad11431 phy: lynx-28g: serialize concurrent phy_set_mode_ext() calls to shared registers
The protocol converter configuration registers PCC8, PCCC, PCCD
(implemented by the driver), as well as others, control protocol
converters from multiple lanes (each represented as a different
struct phy). So, if there are simultaneous calls to phy_set_mode_ext()
to lanes sharing the same PCC register (either for the "old" or for the
"new" protocol), corruption of the values programmed to hardware is
possible, because lynx_28g_rmw() has no locking.

Add a spinlock in the struct lynx_28g_priv shared by all lanes, and take
the global spinlock from the phy_ops :: set_mode() implementation. There
are no other callers which modify PCC registers.

Fixes: 8f73b37cf3fb ("phy: add support for the Layerscape SerDes 28G")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2023-10-06 10:59:52 +01:00
Vladimir Oltean
0ac87fe54a phy: lynx-28g: lock PHY while performing CDR lock workaround
lynx_28g_cdr_lock_check() runs once per second in a workqueue to reset
the lane receiver if the CDR has not locked onto bit transitions in the
RX stream. But the PHY consumer may do stuff with the PHY simultaneously,
and that isn't okay. Block concurrent generic PHY calls by holding the
PHY mutex from this workqueue.

Fixes: 8f73b37cf3fb ("phy: add support for the Layerscape SerDes 28G")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2023-10-06 10:59:52 +01:00
Ioana Ciornei
f200bab375 phy: lynx-28g: cancel the CDR check work item on the remove path
The blamed commit added the CDR check work item but didn't cancel it on
the remove path. Fix this by adding a remove function which takes care
of it.

Fixes: 8f73b37cf3fb ("phy: add support for the Layerscape SerDes 28G")
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2023-10-06 10:59:52 +01:00
Geert Uytterhoeven
089667aaaa phy: realtek: Realtek PHYs should depend on ARCH_REALTEK
The Realtek SoC USB2 and USB3 PHY Transceivers are only present on
Realtek Digital Home Center (DHC) RTD series SoCs.  Hence add a
dependency on ARCH_REALTEK, to prevent asking the user about these
drivers when configuring a kernel without Realtek SoC support.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/2892527cac9af6fa8f5e7b8daeffd7d4351fde68.1692113167.git.geert+renesas@glider.be
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-09-29 21:47:37 +05:30
Konrad Dybcio
56156a76e7 phy: qualcomm: phy-qcom-eusb2-repeater: Add tuning overrides
There are devices in the wild, like the Sony Xperia 1 V that *require*
different tuning than the base design for USB to work.

Add support for overriding the necessary tuning values.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230830-topic-eusb2_override-v2-4-7d8c893d93f6@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-09-21 16:38:51 +02:00
Konrad Dybcio
99a517a582 phy: qualcomm: phy-qcom-eusb2-repeater: Zero out untouched tuning regs
The vendor kernel zeroes out all tuning data outside the init sequence
as part of initialization. Follow suit to avoid UB.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230830-topic-eusb2_override-v2-3-7d8c893d93f6@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-09-21 16:38:51 +02:00
Konrad Dybcio
4ba2e52718 phy: qualcomm: phy-qcom-eusb2-repeater: Use regmap_fields
Switch to regmap_fields, so that the values written into registers are
sanitized by their explicit sizes and the different registers are
structured in an iterable object to make external changes to the init
sequence simpler.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230830-topic-eusb2_override-v2-2-7d8c893d93f6@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-09-21 16:38:51 +02:00
Nitheesh Sekar
68320e35f8 phy: qcom-m31: Add compatible, phy init sequence for IPQ5018
Add phy init sequence and compatible string for IPQ5018
chipset.

Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Link: https://lore.kernel.org/r/20230904063635.24975-3-quic_nsekar@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-09-21 16:38:51 +02:00
Bo Liu
11395c32f9 phy: qualcomm: Fix typos in comments
Fix typo in the description of the 'succesfully'.

Signed-off-by: Bo Liu <liubo03@inspur.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230912114646.8452-1-liubo03@inspur.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-09-21 16:24:00 +02:00
Konrad Dybcio
76d20290d0 phy: qcom-qmp-combo: initialize PCS_USB registers
Currently, PCS_USB registers that have their initialization data in a
pcs_usb_tbl table are never initialized. Fix that.

Fixes: fc64623637da ("phy: qcom-qmp-combo,usb: add support for separate PCS_USB region")
Reported-by: Adrien Thierry <athierry@redhat.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230829-topic-8550_usbphy-v3-2-34ec434194c5@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-09-21 16:23:13 +02:00
Konrad Dybcio
112c23705c phy: qcom-qmp-combo: Square out 8550 POWER_STATE_CONFIG1
There are two instances of the POWER_STATE_CONFIG1 register: one in
the PCS space and another one in PCS_USB.

The downstream init sequence pokes the latter one while we've been poking
the former one (and misnamed it as the latter one, impostor!). Fix that
up to avoid UB.

Fixes: 49742e9edab3 ("phy: qcom-qmp-combo: Add support for SM8550")
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230829-topic-8550_usbphy-v3-1-34ec434194c5@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-09-21 16:23:13 +02:00
Varadarajan Narayanan
ecec1de5c5 phy: qcom: m31: Remove unwanted qphy->vreg is NULL check
Fix the following Smatch complaint:
	drivers/phy/qualcomm/phy-qcom-m31.c:175 m31usb_phy_init()
	warn: variable dereferenced before check 'qphy->vreg' (see line 167)

drivers/phy/qualcomm/phy-qcom-m31.c
   166
   167		ret = regulator_enable(qphy->vreg);
                                       ^^^^^^^^^^
Unchecked dereference

   168		if (ret) {
   169			dev_err(&phy->dev, "failed to enable regulator, %d\n", ret);
   170			return ret;
   171		}
   172
   173		ret = clk_prepare_enable(qphy->clk);
   174		if (ret) {
   175			if (qphy->vreg)
                            ^^^^^^^^^^
Checked too late

   176				regulator_disable(qphy->vreg);
   177			dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);

Since the phy will not get registered if qphy->vreg is NULL,
this check is not needed.

Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
Closes: https://lore.kernel.org/linux-phy/cbd26132-c624-44b7-a073-73222b287338@moroto.mountain/T/#u
Fixes: 08e49af50701 ("phy: qcom: Introduce M31 USB PHY driver")
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/1694069452-3794-1-git-send-email-quic_varada@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-09-21 16:18:22 +02:00
Jinjie Ruan
6ee8a9a772 phy: realtek: usb: Drop unnecessary error check for debugfs_create_dir()
Both debugfs_create_dir() and debugfs_create_file() return ERR_PTR
and never return NULL.

As Greg suggested, this patch removes the error checking for
debugfs_create_dir in phy-rtk-usb2.c and phy-rtk-usb3.c. This is because
the DebugFS kernel API is developed in a way that the caller can safely
ignore the errors that occur during the creation of DebugFS nodes. The
debugfs APIs have a IS_ERR() judge in start_creating() which can handle it
gracefully. So these checks are unnecessary.

Fixes: 134e6d25f6bd ("phy: realtek: usb: Add driver for the Realtek SoC USB 2.0 PHY")
Fixes: adda6e82a7de ("phy: realtek: usb: Add driver for the Realtek SoC USB 3.0 PHY")
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Suggested-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Link: https://lore.kernel.org/r/20230901075231.1368947-1-ruanjinjie@huawei.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-09-21 16:14:22 +02:00
Yang Yingliang
426e05ce12 phy: qcom: phy-qcom-m31: change m31_ipq5332_regs to static
m31_ipq5332_regs is only used in phy-qcom-m31.c now, change
it to static.

Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20230824092356.1154839-1-yangyingliang@huawei.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-09-21 16:05:30 +02:00