272 Commits

Author SHA1 Message Date
Kuninori Morimoto
36fb7b8af5 pinctrl: renesas: r8a779g0: Add missing MODSELx for TSN0
TSN0 needs MODSEL4 settings.
This patch adds missing MODSELx settings for the affected pins.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87letdsj8e.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:12:37 +02:00
Kuninori Morimoto
b811062e5f pinctrl: renesas: r8a779g0: Add missing ERROROUTC_A
This patch adds missing ERROROUTC_A settings.
Current existing ERROROUTC should be _B, this patch tidies it up.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87mtdtsj8m.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:12:37 +02:00
Kuninori Morimoto
c606c2fde2 pinctrl: renesas: r8a779g0: Add missing PWM
R-Car V4H has PWM/PWM_A/PWM_B, but current PFC setting is mixed.
This patch adds missing PWM settings, and tidies these up.

According to Document, GP3_14 Function4 is PWM2_A,
but we can't select it at P1SR3[27:24].
This patch just ignore it for now.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87o7y9sj90.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:12:37 +02:00
Kuninori Morimoto
1c2646b5ce pinctrl: renesas: r8a779g0: Add missing FlexRay
This patch adds missing FlexRay pins.
Because Document (Rev.0.51) has 2x FXR_TXENA/B pin with no suffix (_A, _B),
this patch names them as _X.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87pmipsj9a.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:12:37 +02:00
Kuninori Morimoto
85a9cbe4c5 pinctrl: renesas: r8a779g0: Add missing TPU0TOx_A
This patch adds missing TPU0TOx_A.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87r135sj9j.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:12:37 +02:00
Kuninori Morimoto
c2b4b2cd63 pinctrl: renesas: r8a779g0: Add missing CANFD5_B
This patch adds missing CANFD5_B.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87sfnlsj9t.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:12:37 +02:00
Kuninori Morimoto
9c151c2be9 pinctrl: renesas: r8a779g0: Add missing SCIF1_X
This patch adds missing SCIF1_X.
Because Document (Rev.0.51) has 2x SCIF1 with no suffix (_A, _B),
this patch names it as _X.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87tu81sja1.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:12:37 +02:00
Kuninori Morimoto
49e4697656 pinctrl: renesas: r8a779g0: Add missing SCIF3
R-Car V4H has SCIF3 and SCIF3_A, but current PFC setting is mixed.
This patch cleans up SCIF3/SCIF3_A, based on Rev.0.51.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87v8shsja7.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:12:37 +02:00
Kuninori Morimoto
cf4f789184 pinctrl: renesas: r8a779g0: Add missing HSCIF1_X
This patch adds missing HSCIF1.
Because Document (Rev.0.51) has 2x HSCIF1 with no suffix (_A, _B),
this patch names it as _X.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87wncxsjah.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:12:37 +02:00
Kuninori Morimoto
213b713255 pinctrl: renesas: r8a779g0: Add missing HSCIF3_A
This patch adds missing HSCIF3_A.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87y1xdsjar.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:12:37 +02:00
Kuninori Morimoto
1b23d8a478 pinctrl: renesas: r8a779g0: Add missing IRQx_A/IRQx_B
This patch adds missing IRQx_A/IRQx_B, and tidies up existing IRQs.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87zghtsjb4.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:12:37 +02:00
Kuninori Morimoto
0df46188a5 pinctrl: renesas: r8a779g0: Add missing TCLKx_A/TCLKx_B/TCLKx_X
This patch adds missing TCLKx_A/TCLKx_B/TCLKx_X.

Because Document (Rev.0.51) has 2x TCLK3/TCLK4 with no suffix (_A, _B),
this patch names them as _X.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/871qv5txvt.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:12:37 +02:00
Kuninori Morimoto
475425ee38 pinctrl: renesas: r8a779g0: Tidyup POC1 voltage
According to Rev.0.51 datasheet 004_R-CarV4H_pin_function.xlsx,
GP1_23 - GP1_28 are 1.8/3.3V.  But they are not on Table 7.28.
According to the HW team, there are no bits assigned.
This patch follows HW team's comment.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/8735fltxwg.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:12:37 +02:00
Kuninori Morimoto
5a494f02b8 pinctrl: renesas: r8a779g0: Tidy up ioctrl_regs
Remove POC2 which is not documented, and remove TD0SEL3 which is not
needed.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/874k01txy9.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:12:37 +02:00
Kuninori Morimoto
b279b54b50 pinctrl: renesas: r8a779g0: Remove unused MOD_SELx definitions
Current R-Car V4H PFC code has many MOD_SELx definitions with all 0.
But these have no meaning.  This patch removes them.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/875ykhtxym.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:12:36 +02:00
Kuninori Morimoto
1204bc463b pinctrl: renesas: r8a779g0: Remove unused IPxSRx definitions
Current R-Car V4H PFC code has many IPxSRx definitions with all 0.
But these have no meaning.  This patch removes them.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/877d4xtxyv.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:12:36 +02:00
Kuninori Morimoto
aa83be7c8d pinctrl: renesas: r8a779g0: Remove unused NOGP definitions
Current R-Car V4H PFC code has many NOGP definitions.  But these are not
used, and they are different from original usage.  This patch removes
them.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/878rpdtxz8.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:12:36 +02:00
Kuninori Morimoto
42cbd16e7c pinctrl: renesas: r8a779g0: Fixup MODSEL8
MODSEL8 controls I2C vs. GPIO modes, and the Datasheet (Rev.0.51) is
indicating that I2C needs 1.  But we should use 0 for all cases in
reality.  New Datasheet should be updated.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87a69ttxzg.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:12:36 +02:00
Phong Hoang
050442ae4c pinctrl: renesas: r8a779g0: Add pins, groups and functions
This patch adds SCIF, I2C, EthernetAVB, HSCIF, MMC, QSPI, MSIOF, PWM,
CAN-FD, Ethernet-TSN, PCIe pins, groups, and functions.

This patch was created based on the Rev.0.51 datasheet.

Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com>
Signed-off-by: CongDang <cong.dang.xn@renesas.com>
Signed-off-by: Kazuya Mizuguch <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Tho Vu <tho.vu.wh@renesas.com>
[Morimoto: merged above patches into one, cleanup white space, sort modules alphabetically, fixup comments]
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87bku9ty0b.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:12:36 +02:00
LUU HOAI
ad9bb2fec6 pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support
This patch adds initial pinctrl support for the R-Car V4H (R8A779G0)
SoC, including bias, drive strength and voltage control.

This patch was created based on the Rev.0.51 datasheet.

Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[Morimoto: merge Kihara-san's MODSEL8 fixup patch, cleanup white space, care about reserved bits on each configs, fixup comments, etc.]
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87czepty0j.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:12:36 +02:00
Kuninori Morimoto
665f77eb0d pinctrl: renesas: Add PORT_GP_CFG_13 macros
Add PORT_GP_CFG_13() and PORT_GP_13() helper macros, to be used by the
r8a779g0 subdriver.

Based on a larger patch in the BSP by LUU HOAI.

Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87edz5ty0r.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:12:36 +02:00
Phil Edworthy
92a9b82525 pinctrl: renesas: Add RZ/V2M pin and gpio controller driver
Add support for pin and gpio controller driver for RZ/V2M SoC.
Based on the RZ/G2L driver.

Note that the DETDO and DETMS dedicated pins are currently not
documented in the HW manual as to which pin group they are in.
HW team has since said that the output level of 1.8V I/O group 4
(for MD0-7, and debugger) is the same as the 1.8V I/O group 3.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220624084833.22605-3-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:12:36 +02:00
Geert Uytterhoeven
2f805cba10 pinctrl: renesas: r8a779f0: Remove unused POC2
The POWER Condition Control Register 2 (POC2) is unused, and the
documentation does not define any valid bits.  Remove it.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/d8a9ea39b49d24e39f4da3f00b64bce34016887d.1655301529.git.geert+renesas@glider.be
2022-06-29 15:53:04 +02:00
Lad Prabhakar
5223c511eb pinctrl: renesas: rzg2l: Return -EINVAL for pins which have input disabled
Pin status reported by pinconf-pins file always reported pin status as
"input enabled" even for pins which had input disabled. Fix this by
returning -EINVAL for the pins which have input disabled.

Fixes: c4c4637eb57f2 ("pinctrl: renesas: Add RZ/G2L pin and gpio controller driver")
Reported-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com>
Link: https://lore.kernel.org/r/20220511094057.3151-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-06 11:12:22 +02:00
Linus Walleij
7755d26c04 pinctrl: renesas: Updates for v5.19 (take two)
- Reserved field optimizations,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-pinctrl-for-v5.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v5.19 (take two)

  - Reserved field optimizations,
  - Miscellaneous fixes and improvements.
2022-05-14 01:01:56 +02:00
Geert Uytterhoeven
fc883ed5a4 pinctrl: renesas: checker: Add reserved field checks
Add checks for discovering registers with reserved fields that could
benefit from being described using variable-width reserved field
shorthands, reducing kernel size.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f5a5159ba7b396e6f09dd3f23c864a74ed8e342d.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:28 +02:00
Geert Uytterhoeven
753278b4cb pinctrl: renesas: sh7786: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 79 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/22487451ff7d8cce0182354c9553f3b171cc34d9.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:28 +02:00
Geert Uytterhoeven
63a32f8286 pinctrl: renesas: sh7785: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 150 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/07a238f13f80674d86719a5e869c65a2e0b8c1c1.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:28 +02:00
Geert Uytterhoeven
2439a0dde4 pinctrl: renesas: sh7757: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 115 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/05c69ca8710134bb96ec8f7d18bafe42418f3510.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:28 +02:00
Geert Uytterhoeven
3a0a3c1be8 pinctrl: renesas: sh7734: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 161 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/18e476c0a9f0af5b5d511d1c4922c6e299d1847a.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:28 +02:00
Geert Uytterhoeven
2a1b67b565 pinctrl: renesas: sh7724: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 8 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/696dcad42a8b8395276301eb5dd5c5a895826f35.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:28 +02:00
Geert Uytterhoeven
98edc79d9a pinctrl: renesas: sh7723: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 105 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/5d7ef2fa02c2137d2d243fc183d18220c9aaf7b8.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:28 +02:00
Geert Uytterhoeven
72db29175f pinctrl: renesas: sh7722: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 396 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c3965b6f9ea603b185924136f859c6eca7d5d6f4.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:28 +02:00
Geert Uytterhoeven
aa9c0a767f pinctrl: renesas: sh7720: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 128 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/4b290f93a7edb1f91c97da90e67b7f6f3df62951.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:28 +02:00
Geert Uytterhoeven
064aa9aabe pinctrl: renesas: sh73a0: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 154 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/e74738b403cc15b3407e7568d323fdae8e7b30dd.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:28 +02:00
Geert Uytterhoeven
d567210e4b pinctrl: renesas: sh7269: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 406 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/feb1e865c2b6abbc0db24243143ea09ad143f6df.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:28 +02:00
Geert Uytterhoeven
78fc20c155 pinctrl: renesas: sh7264: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 572 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/434c274f626b2eab3539fe2ab80c6eda164e07fa.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:28 +02:00
Geert Uytterhoeven
256c14196f pinctrl: renesas: sh7203: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 281 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c625b4eee298b88c2ee47ed80b0dea5d02ed56d1.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:27 +02:00
Geert Uytterhoeven
170285f4c5 pinctrl: renesas: r8a779f0: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 183 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/e50f9c8ef1261b7ceb6b1be637d4019fe7312250.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:27 +02:00
Geert Uytterhoeven
b9f01b20cc pinctrl: renesas: r8a779a0: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 556 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/7db3751ecf96fcc469bd14eeb02d69e565956151.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:27 +02:00
Geert Uytterhoeven
ec255e1c15 pinctrl: renesas: r8a77995: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 422 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/d74af80fdb7b6d78b10634238a88e55a139e5c22.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:27 +02:00
Geert Uytterhoeven
be525de9e8 pinctrl: renesas: r8a77990: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 226 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/924ba4505e33180e078ca72a1db8db13c193cbea.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:27 +02:00
Geert Uytterhoeven
23dbafd819 pinctrl: renesas: r8a77980: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 198 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/0bf6b069a794b3c56c0c9311ac4b2ada577a9cb7.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:27 +02:00
Geert Uytterhoeven
37362c77de pinctrl: renesas: r8a77970: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 268 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/33dd9bc41df888f132e2e6921d2ff38225b68105.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:27 +02:00
Geert Uytterhoeven
34856c5029 pinctrl: renesas: r8a7796: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 496 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/81f3586749bb1117c5636e9a9663d25e77cbe158.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:27 +02:00
Geert Uytterhoeven
efd5ee63e9 pinctrl: renesas: r8a77965: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 496 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/2aff2f4c1ed6d834370ce6dd9379c8c93bfc0a92.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:27 +02:00
Geert Uytterhoeven
d5ea70ead8 pinctrl: renesas: r8a77951: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 496 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/cd59cc2e0f55f0dcede1356f73a9e69fe09bf5eb.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:27 +02:00
Geert Uytterhoeven
8e8fb81292 pinctrl: renesas: r8a77950: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 473 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/a1617d24af2b9b3224ce84c0ada535565009fdda.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:27 +02:00
Geert Uytterhoeven
5b7dda3a49 pinctrl: renesas: r8a7792: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 257 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/0f211d493a0cfbcd96d84a709d21bea51c7385ae.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:27 +02:00
Geert Uytterhoeven
9794156d6b pinctrl: renesas: r8a7779: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 81 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/ecc7377d2992694226dcf055bed0b617701a3d71.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:27 +02:00