965 Commits

Author SHA1 Message Date
Vladimir Zapolskiy
f8acf01a6a clk: qcom: camcc-sm8250: Fix topology around titan_top power domain
On SM8250 two found VFE GDSC power domains shall not be operated, if
titan top is turned off, thus the former power domains will be set as
subdomains by a GDSC registration routine.

Fixes: 5d66ca79b58c ("clk: qcom: Add camera clock controller driver for SM8250")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220519214133.1728979-3-vladimir.zapolskiy@linaro.org
2022-06-30 18:34:55 -05:00
Vladimir Zapolskiy
103dd2338b clk: qcom: camcc-sdm845: Fix topology around titan_top power domain
On SDM845 two found VFE GDSC power domains shall not be operated, if
titan top is turned off, thus the former power domains will be set as
subdomains by a GDSC registration routine.

Fixes: 78412c262004 ("clk: qcom: Add camera clock controller driver for SDM845")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220519214133.1728979-2-vladimir.zapolskiy@linaro.org
2022-06-30 18:34:54 -05:00
Robert Marko
1bf7305e79 clk: qcom: ipq8074: dont disable gcc_sleep_clk_src
Once the usb sleep clocks are disabled, clock framework is trying to
disable the sleep clock source also.

However, it seems that it cannot be disabled and trying to do so produces:
[  245.436390] ------------[ cut here ]------------
[  245.441233] gcc_sleep_clk_src status stuck at 'on'
[  245.441254] WARNING: CPU: 2 PID: 223 at clk_branch_wait+0x130/0x140
[  245.450435] Modules linked in: xhci_plat_hcd xhci_hcd dwc3 dwc3_qcom leds_gpio
[  245.456601] CPU: 2 PID: 223 Comm: sh Not tainted 5.18.0-rc4 #215
[  245.463889] Hardware name: Xiaomi AX9000 (DT)
[  245.470050] pstate: 204000c5 (nzCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[  245.474307] pc : clk_branch_wait+0x130/0x140
[  245.481073] lr : clk_branch_wait+0x130/0x140
[  245.485588] sp : ffffffc009f2bad0
[  245.489838] x29: ffffffc009f2bad0 x28: ffffff8003e6c800 x27: 0000000000000000
[  245.493057] x26: 0000000000000000 x25: 0000000000000000 x24: ffffff800226ef20
[  245.500175] x23: ffffffc0089ff550 x22: 0000000000000000 x21: ffffffc008476ad0
[  245.507294] x20: 0000000000000000 x19: ffffffc00965ac70 x18: fffffffffffc51a7
[  245.514413] x17: 68702e3030303837 x16: 3a6d726f6674616c x15: ffffffc089f2b777
[  245.521531] x14: ffffffc0095c9d18 x13: 0000000000000129 x12: 0000000000000129
[  245.528649] x11: 00000000ffffffea x10: ffffffc009621d18 x9 : 0000000000000001
[  245.535767] x8 : 0000000000000001 x7 : 0000000000017fe8 x6 : 0000000000000001
[  245.542885] x5 : ffffff803fdca6d8 x4 : 0000000000000000 x3 : 0000000000000027
[  245.550002] x2 : 0000000000000027 x1 : 0000000000000023 x0 : 0000000000000026
[  245.557122] Call trace:
[  245.564229]  clk_branch_wait+0x130/0x140
[  245.566490]  clk_branch2_disable+0x2c/0x40
[  245.570656]  clk_core_disable+0x60/0xb0
[  245.574561]  clk_core_disable+0x68/0xb0
[  245.578293]  clk_disable+0x30/0x50
[  245.582113]  dwc3_qcom_remove+0x60/0xc0 [dwc3_qcom]
[  245.585588]  platform_remove+0x28/0x60
[  245.590361]  device_remove+0x4c/0x80
[  245.594179]  device_release_driver_internal+0x1dc/0x230
[  245.597914]  device_driver_detach+0x18/0x30
[  245.602861]  unbind_store+0xec/0x110
[  245.607027]  drv_attr_store+0x24/0x40
[  245.610847]  sysfs_kf_write+0x44/0x60
[  245.614405]  kernfs_fop_write_iter+0x128/0x1c0
[  245.618052]  new_sync_write+0xc0/0x130
[  245.622391]  vfs_write+0x1d4/0x2a0
[  245.626123]  ksys_write+0x58/0xe0
[  245.629508]  __arm64_sys_write+0x1c/0x30
[  245.632895]  invoke_syscall.constprop.0+0x5c/0x110
[  245.636890]  do_el0_svc+0xa0/0x150
[  245.641488]  el0_svc+0x18/0x60
[  245.644872]  el0t_64_sync_handler+0xa4/0x130
[  245.647914]  el0t_64_sync+0x174/0x178
[  245.652340] ---[ end trace 0000000000000000 ]---

So, add CLK_IS_CRITICAL flag to the clock so that the kernel won't try
to disable the sleep clock.

Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-10-robimarko@gmail.com
2022-06-30 18:24:54 -05:00
Robert Marko
8add990ace clk: qcom: ipq8074: add USB GDSCs
Add GDSC-s for each of the two USB controllers built-in the IPQ8074.

Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-9-robimarko@gmail.com
2022-06-30 18:24:54 -05:00
Robert Marko
2bd357e698 clk: qcom: ipq8074: set BRANCH_HALT_DELAY flag for UBI clocks
Currently, attempting to enable the UBI clocks will cause the stuck at
off warning to be printed and clk_enable will fail.

[   14.936694] gcc_ubi1_ahb_clk status stuck at 'off'

Downstream 5.4 QCA kernel has fixed this by seting the BRANCH_HALT_DELAY
flag on UBI clocks, so lets do the same.

Fixes: 5736294aef83 ("clk: qcom: ipq8074: add NSS clocks")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-6-robimarko@gmail.com
2022-06-30 18:06:13 -05:00
Robert Marko
74521205b6 clk: qcom: ipq8074: add PPE crypto clock
The built-in PPE engine has a dedicated clock for the EIP-197 crypto
engine.

So, since the required clock currently missing add support for it.

Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-5-robimarko@gmail.com
2022-06-30 18:06:13 -05:00
Robert Marko
0e9e61a281 clk: qcom: ipq8074: fix NSS port frequency tables
NSS port 5 and 6 frequency tables are currently broken and are causing a
wide ranges of issue like 1G not working at all on port 6 or port 5 being
clocked with 312 instead of 125 MHz as UNIPHY1 gets selected.

So, update the frequency tables with the ones from the downstream QCA 5.4
based kernel which has already fixed this.

Fixes: 7117a51ed303 ("clk: qcom: ipq8074: add NSS ethernet port clocks")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-3-robimarko@gmail.com
2022-06-30 18:06:13 -05:00
Robert Marko
3401ea2856 clk: qcom: ipq8074: SW workaround for UBI32 PLL lock
UBI32 Huayra PLL fails to lock in 5 us in some SoC silicon and thus it
will cause the wait_for_pll() to timeout and thus return the error
indicating that the PLL failed to lock.

This is bug in Huayra PLL HW for which SW workaround
is to set bit 26 of TEST_CTL register.

This is ported from the QCA 5.4 based downstream kernel.

Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-2-robimarko@gmail.com
2022-06-30 18:06:13 -05:00
Robert Marko
ca41ec1b30 clk: qcom: ipq8074: fix NSS core PLL-s
Like in IPQ6018 the NSS related Alpha PLL-s require initial configuration
to work.

So, obtain the regmap that is required for the Alpha PLL configuration
and thus utilize the qcom_cc_really_probe() as we already have the regmap.
Then utilize the Alpha PLL configs from the downstream QCA 5.4 based
kernel to configure them.

This fixes the UBI32 and NSS crypto PLL-s failing to get enabled by the
kernel.

Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-1-robimarko@gmail.com
2022-06-30 18:06:13 -05:00
Bryan O'Donoghue
05eed09909 clk: qcom: gcc-msm8939: Point MM peripherals to system_mm_noc clock
Qcom docs indciate the following peripherals operating from System NOC
MM not from System NOC clocks.

- MDP
- VFE
- JPEGe
- Venus

Switch over the relevant parent pointers.

Fixes: 1664014e4679 ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller")
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220504163835.40130-5-bryan.odonoghue@linaro.org
2022-06-29 22:47:38 -05:00
Bryan O'Donoghue
dd363e2f71 clk: qcom: gcc-msm8939: Add missing system_mm_noc_bfdcd_clk_src
The msm8939 has an additional higher operating point for the multi-media
peripherals. The higher throughput MM componets operate off of the
system-mm noc not the system noc.

system_mm_noc_bfdcd_clk_src is the source clock for the higher frequency
capable system noc mm.

Maximum frequency for the MM SNOC is 400 MHz.

Fixes: 1664014e4679 ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller")
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220504163835.40130-4-bryan.odonoghue@linaro.org
2022-06-29 22:47:31 -05:00
Bryan O'Donoghue
63d4270832 clk: qcom: gcc-msm8939: Fix bimc_ddr_clk_src rcgr base address
Reviewing qcom docs for the 8939 we can see the command rcgr is pointing to
the wrong address. bimc_ddr_clk_src_rcgr is @ 0x01832024 not 0x01832004.

Fixes: 1664014e4679 ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller")
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220504163835.40130-3-bryan.odonoghue@linaro.org
2022-06-29 22:47:23 -05:00
Johan Hovold
9410fb9401 clk: qcom: gcc-sc8280xp: use phy-mux clock for PCIe
Use the new phy-mux clock implementation for the PCIe pipe clock muxes
so that the pipe clock source is set to the QMP PHY PLL when the
downstream pipe clock is enabled and restored to the always-on XO when
it is again disabled.

This is needed to prevent the corresponding GDSC from hanging when
enabling or disabling the PCIe power domain, something which requires a
ticking source.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220628085707.16214-1-johan+linaro@kernel.org
2022-06-29 21:53:23 -05:00
Ansuel Smith
898d0d6483 clk: qcom: clk-krait: add apq/ipq8064 errata workaround
Add apq/ipq8064 errata workaround where the sec_src clock gating needs to
be disabled during switching. krait-cc compatible is not enough to
handle this and limit this workaround to apq/ipq8064. We check machine
compatible to handle this.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220430054458.31321-4-ansuelsmth@gmail.com
2022-06-27 15:41:37 -05:00
Ansuel Smith
df83d2c9e7 clk: qcom: clk-krait: unlock spin after mux completion
Unlock spinlock after the mux switch is completed to prevent any corner
case of mux request while the switch still needs to be done.

Fixes: 4d7dc77babfe ("clk: qcom: Add support for Krait clocks")
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220430054458.31321-3-ansuelsmth@gmail.com
2022-06-27 15:41:37 -05:00
Ansuel Smith
fcfbfe373d clk: qcom: clk-hfpll: use poll_timeout macro
Use regmap_read_poll_timeout macro instead of do-while structure to tidy
things up. Also set a timeout to prevent any sort of system stall.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220430054458.31321-2-ansuelsmth@gmail.com
2022-06-27 15:41:37 -05:00
Li kunyu
255a47e745 clk: qcom: gcc-sm6350: Drop extra semicolon
Drop the extra semicolon after qcom_cc_really_probe()

Signed-off-by: Li kunyu <kunyu@nfschina.com>
[bjorn: Rewrote commit message]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220627020500.135125-1-kunyu@nfschina.com
2022-06-27 15:11:48 -05:00
Johan Hovold
8d114b94fc clk: qcom: gcc-sc8280xp: use collapse-voting for PCIe GDSCs
The PCIe GDSCs can be shared with other masters and should use the APCS
collapse-vote register when updating the power state.

This is specifically also needed to be able to disable power domains
that have been enabled by boot firmware using the vote register.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220520100948.19622-4-johan+linaro@kernel.org
2022-06-25 22:38:02 -05:00
Johan Hovold
77ea2bd72d clk: qcom: gdsc: add support for collapse-vote registers
Recent Qualcomm platforms have APCS collapse-vote registers that allow
for sharing GDSCs with other masters (e.g. LPASS).

Add support for using such vote registers instead of the control
register when updating the GDSC power state.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220520100948.19622-3-johan+linaro@kernel.org
2022-06-25 22:38:02 -05:00
Johan Hovold
e73cb8527c clk: qcom: gdsc: add collapse-bit helper
Add a helper for updating the SW_COLLAPSE bit during initialisation and
state updates.

Note that the update during initialisation was relying on the
SW_COLLAPSE bit not having been set earlier rather than passing in zero
explicitly to clear the collapse vote.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220520100948.19622-2-johan+linaro@kernel.org
2022-06-25 22:38:02 -05:00
Vladimir Zapolskiy
c4f4035190 clk: qcom: camcc-sm8250: Fix halt on boot by reducing driver's init level
Access to I/O of SM8250 camera clock controller IP depends on enabled
GCC_CAMERA_AHB_CLK clock supplied by global clock controller, the latter
one is inited on subsys level, so, to satisfy the dependency, it would
make sense to deprive the init level of camcc-sm8250 driver.

If both drivers are compiled as built-in, there is a change that a board
won't boot up due to a race, which happens on the same init level.

Fixes: 5d66ca79b58c ("clk: qcom: Add camera clock controller driver for SM8250")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220518103554.949511-1-vladimir.zapolskiy@linaro.org
2022-06-25 22:07:53 -05:00
Bjorn Andersson
1ecbc2b37f v5.19-rc1 +
20220608105238.2973600-2-dmitry.baryshkov@linaro.org +
 20220608105238.2973600-3-dmitry.baryshkov@linaro.org +
 20220608105238.2973600-4-dmitry.baryshkov@linaro.org
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Merge tag '20220608105238.2973600-1-dmitry.baryshkov@linaro.org' into clk-for-5.20

v5.19-rc1 +
20220608105238.2973600-2-dmitry.baryshkov@linaro.org +
20220608105238.2973600-3-dmitry.baryshkov@linaro.org +
20220608105238.2973600-4-dmitry.baryshkov@linaro.org
2022-06-25 21:38:04 -05:00
Dmitry Baryshkov
553d12b20c clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe clocks
Use newly defined clk_regmap_phy_mux_ops for PCIe pipe clocks to let
the clock framework automatically park the clock when the clock is
switched off and restore the parent when the clock is switched on.

Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220608105238.2973600-4-dmitry.baryshkov@linaro.org
2022-06-25 21:36:08 -05:00
Dmitry Baryshkov
7ee9d2e8b9 clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe clocks
Use newly defined clk_regmap_phy_mux_ops for PCIe pipe clocks to let
the clock framework automatically park the clock when the clock is
switched off and restore the parent when the clock is switched on.

Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220608105238.2973600-3-dmitry.baryshkov@linaro.org
2022-06-25 21:36:08 -05:00
Dmitry Baryshkov
74e4190cde clk: qcom: regmap: add PHY clock source implementation
On recent Qualcomm platforms the QMP PIPE clocks feed into a set of
muxes which must be parked to the "safe" source (bi_tcxo) when
corresponding GDSC is turned off and on again. Currently this is
handcoded in the PCIe driver by reparenting the gcc_pipe_N_clk_src
clock. However the same code sequence should be applied in the
pcie-qcom endpoint, USB3 and UFS drivers.

Rather than copying this sequence over and over again, follow the
example of clk_rcg2_shared_ops and implement this parking in the
enable() and disable() clock operations. Supplement the regmap-mux with
the new clk_regmap_phy_mux type, which implements such multiplexers
as a simple gate clocks.

This is possible since each of these multiplexers has just two clock
sources: one coming from the PHY and a reference (XO) one.  If the clock
is running off the from-PHY source, report it as enabled. Report it as
disabled otherwise (if it uses reference source).

This way the PHY will disable the pipe clock before turning off the
GDSC, which in turn would lead to disabling corresponding pipe_clk_src
(and thus it being parked to a safe, reference clock source). And vice
versa, after enabling the GDSC the PHY will enable the pipe clock, which
would cause pipe_clk_src to be switched from a safe source to the
working one.

Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220608105238.2973600-2-dmitry.baryshkov@linaro.org
2022-06-25 21:36:07 -05:00
Dmitry Baryshkov
e7c659124c clk: qcom: mmcc-msm8996: use parent_hws/_data instead of parent_names
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220617122922.769562-6-dmitry.baryshkov@linaro.org
2022-06-25 15:18:15 -05:00
Dmitry Baryshkov
208c564fe6 clk: qcom: mmcc-msm8996: move clock parent tables down
Move clock parent tables down, after the MMPLL declrataions, so that we
can use gpll hw clock fields in the next commit.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220617122922.769562-5-dmitry.baryshkov@linaro.org
2022-06-25 15:17:52 -05:00
Dmitry Baryshkov
a7a4fc9498 clk: qcom: mmcc-msm8996: use ARRAY_SIZE instead of specifying num_parents
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220617122922.769562-4-dmitry.baryshkov@linaro.org
2022-06-25 15:17:30 -05:00
Stephen Boyd
29f66b6252 clk: qcom: rpmh: Add note about sleep/wake state for BCMs
The sleep/wake state doesn't need to be set here because of specific
RPMh behavior that carries over the active state when sleep/wake state
hasn't been modified. Add a note to the code so we aren't tempted to set
the sleep/wake states.

Cc: Alex Elder <elder@linaro.org>
Cc: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Alex Elder <elder@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220517190949.2922197-1-swboyd@chromium.org
2022-06-25 15:00:56 -05:00
Linus Torvalds
6b0e34a030 Mainly driver updates this time around. There's a single patch to the core clk
framework that simplifies a runtime PM call. Otherwise the majority of the diff
 falls to a few SoC drivers: Qualcomm, STM32 and MediaTek. Those SoCs gain some
 new hardware support and what comes along with that is quite a few lines of
 data and some clk_ops code. Beyond the new hardware support we have the usual
 pile of driver updates that add missing clks on already supported SoCs or fix
 up problems like bad clk tree descriptions. It's nice to see that more drivers
 are moving to clk_hw based APIs too.
 
 New Drivers:
  - Add STM32MP13 RCC driver (Reset Clock Controller)
  - MediaTek MT8186 SoC clk support
  - Airoha EN7523 SoC system clocks
  - Clock driver for exynosautov9 SoC
  - Renesas R-Car V4H and RZ/V2M SoCs
  - Renesas RZ/G2UL SoC
  - LPASS clk driver for Qualcomm sc7280 SoC
  - GCC clk driver for Qualcomm SC8280XP SoC
 
 Updates:
  - SDCC uses floor clk ops on Qualcomm MSM8976
  - Add modem reset and fix RPM clks on Qualcomm MSM8976
  - Add the two missing CLKOUT clocks for U8500/DB8500 SoC
  - Mark some clks critical on Ingenic X1000
  - Convert ux500 to clk_hw
  - Move MediaTek driver to clk_hw provider APIs
  - Use i2c driver probe_new to avoid id scans
  - Convert a number of Rockchip dt bindings to YAML
  - Mark hclk_vo critical on Rockchip rk3568
  - Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage
  - Various cleanups like memory allocation error checks and plugged leaks
  - Allwinner H6 RTC clock support
  - Allwinner H616 32 kHz clock support
  - Add the Universal Flash Storage clock on Renesas R-Car S4-8
  - Add I2C, SSIF-2 (sound), USB, CANFD, OSTM (timer), WDT, SPI Multi
    I/O Bus, RSPI, TSU (thermal), and ADC clocks and resets on Renesas RZ/G2UL
  - Add display clock support on Renesas RZ/G2L
  - Add RPC (QSPI/HyperFlash) clocks on Renesas R-Car E3 and D3
  - Add 27 MHz phy PLL ref clock on i.MX
  - Add mcore_booted module parameter to tell kernel M core has already booted
    for i.MX
  - Remove snvs clock on i.MX because it was for secure world only
  - Add dt bindings for i.MX8MN GPT
  - Add DISP2 pixel clock for i.MX8MP
  - Add clkout1/2 for i.MX8MP
  - Fix parent clock of ubs_root_clk for i.MX8MP
  - Implement better RCG parking on Qualcomm SoCs using the shared RCG clk ops
  - Kerneldoc fixes
  - Switch Tegra BPMP to determine_rate clk op
  - Add a pointer to dt schema for generic clock bindings
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "Mainly driver updates this time around.

  There's a single patch to the core clk framework that simplifies a
  runtime PM call. Otherwise the majority of the diff falls to a few SoC
  drivers: Qualcomm, STM32 and MediaTek. Those SoCs gain some new
  hardware support and what comes along with that is quite a few lines
  of data and some clk_ops code.

  Beyond the new hardware support we have the usual pile of driver
  updates that add missing clks on already supported SoCs or fix up
  problems like bad clk tree descriptions. It's nice to see that more
  drivers are moving to clk_hw based APIs too.

  New Drivers:
   - Add STM32MP13 RCC driver (Reset Clock Controller)
   - MediaTek MT8186 SoC clk support
   - Airoha EN7523 SoC system clocks
   - Clock driver for exynosautov9 SoC
   - Renesas R-Car V4H and RZ/V2M SoCs
   - Renesas RZ/G2UL SoC
   - LPASS clk driver for Qualcomm sc7280 SoC
   - GCC clk driver for Qualcomm SC8280XP SoC

  Updates:
   - SDCC uses floor clk ops on Qualcomm MSM8976
   - Add modem reset and fix RPM clks on Qualcomm MSM8976
   - Add the two missing CLKOUT clocks for U8500/DB8500 SoC
   - Mark some clks critical on Ingenic X1000
   - Convert ux500 to clk_hw
   - Move MediaTek driver to clk_hw provider APIs
   - Use i2c driver probe_new to avoid id scans
   - Convert a number of Rockchip dt bindings to YAML
   - Mark hclk_vo critical on Rockchip rk3568
   - Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage
   - Various cleanups like memory allocation error checks and plugged
     leaks
   - Allwinner H6 RTC clock support
   - Allwinner H616 32 kHz clock support
   - Add the Universal Flash Storage clock on Renesas R-Car S4-8
   - Add I2C, SSIF-2 (sound), USB, CANFD, OSTM (timer), WDT, SPI Multi
     I/O Bus, RSPI, TSU (thermal), and ADC clocks and resets on Renesas
     RZ/G2UL
   - Add display clock support on Renesas RZ/G2L
   - Add RPC (QSPI/HyperFlash) clocks on Renesas R-Car E3 and D3
   - Add 27 MHz phy PLL ref clock on i.MX
   - Add mcore_booted module parameter to tell kernel M core has already
     booted for i.MX
   - Remove snvs clock on i.MX because it was for secure world only
   - Add dt bindings for i.MX8MN GPT
   - Add DISP2 pixel clock for i.MX8MP
   - Add clkout1/2 for i.MX8MP
   - Fix parent clock of ubs_root_clk for i.MX8MP
   - Implement better RCG parking on Qualcomm SoCs using the shared RCG
     clk ops
   - Kerneldoc fixes
   - Switch Tegra BPMP to determine_rate clk op
   - Add a pointer to dt schema for generic clock bindings"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (168 commits)
  Revert "clk: qcom: regmap-mux: add pipe clk implementation"
  Revert "clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks"
  Revert "clk: qcom: gcc-sm8450: use new clk_regmap_mux_safe_ops for PCIe pipe clocks"
  clk: bcm: rpi: Use correct order for the parameters of devm_kcalloc()
  clk: stm32mp13: add safe mux management
  clk: stm32mp13: add multi mux function
  clk: stm32mp13: add all STM32MP13 kernel clocks
  clk: stm32mp13: add all STM32MP13 peripheral clocks
  clk: stm32mp13: manage secured clocks
  clk: stm32mp13: add composite clock
  clk: stm32mp13: add stm32 divider clock
  clk: stm32mp13: add stm32_gate management
  clk: stm32mp13: add stm32_mux clock management
  clk: stm32: Introduce STM32MP13 RCC drivers (Reset Clock Controller)
  dt-bindings: rcc: stm32: add new compatible for STM32MP13 SoC
  clk: ti: clkctrl: replace usage of found with dedicated list iterator variable
  clk: ti: composite: Prefer kcalloc over open coded arithmetic
  dt-bindings: clock: exynosautov9: correct count of NR_CLK
  clk: mediatek: mt8173: Switch to clk_hw provider APIs
  clk: mediatek: Switch to clk_hw provider APIs
  ...
2022-05-27 15:33:24 -07:00
Dmitry Baryshkov
03e053b4f7 Revert "clk: qcom: regmap-mux: add pipe clk implementation"
Johan Hovold has pointed out that there are several deficiencies and a
race condition in the regmap_mux_safe ops that were merged. Pipe clocks
has been updated to use newer and simpler clk_regmap_phy_mux_ops. Drop
the regmap-mux-safe clock ops now.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220521005343.1429642-4-dmitry.baryshkov@linaro.org
2022-05-23 12:26:13 -05:00
Dmitry Baryshkov
720e14f328 Revert "clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks"
Johan Hovold has pointed out that there are several deficiencies and a
race condition in the regmap_mux_safe ops that were merged. Revert the
commit that switches gcc-sc7280 driver to use regmap_mux_safe.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220521005343.1429642-3-dmitry.baryshkov@linaro.org
2022-05-23 12:26:13 -05:00
Dmitry Baryshkov
dd6456e6c4 Revert "clk: qcom: gcc-sm8450: use new clk_regmap_mux_safe_ops for PCIe pipe clocks"
Johan Hovold has pointed out that there are several deficiencies and a
race condition in the regmap_mux_safe ops that were merged. Revert the
commit that switches gcc-sm8450 driver to use regmap_mux_safe.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220521005343.1429642-2-dmitry.baryshkov@linaro.org
2022-05-23 12:26:13 -05:00
Bjorn Andersson
703db1f5da clk: qcom: rcg2: Cache CFG register updates for parked RCGs
As GDSCs are turned on and off some associated clocks are momentarily
enabled for house keeping purposes. For this, and similar, purposes the
"shared RCGs" will park the RCG on a source clock which is known to be
available.
When the RCG is parked, a safe clock source will be selected and
committed, then the original source would be written back and upon enable
the change back to the unparked source would be committed.

But starting with SM8350 this fails, as the value in CFG is committed by
the GDSC handshake and without a ticking parent the GDSC enablement will
time out.

This becomes a concrete problem if the runtime supended state of a
device includes disabling such rcg's parent clock. As the device
attempts to power up the domain again the rcg will fail to enable and
hence the GDSC enablement will fail, preventing the device from
returning from the suspended state.

This can be seen in e.g. the display stack during probe on SM8350.

To avoid this problem, the software needs to ensure that the RCG is
configured to a active parent clock while it is disabled. This is done
by caching the CFG register content while the shared RCG is parked on
this safe source.

Writes to M, N and D registers are committed as they are requested. New
helpers for get_parent() and recalc_rate() are extracted from their
previous implementations and __clk_rcg2_configure() is modified to allow
it to operate on the cached value.

Fixes: 7ef6f11887bd ("clk: qcom: Configure the RCGs to a safe source as needed")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20220426212136.1543984-1-bjorn.andersson@linaro.org
2022-05-19 16:42:30 -05:00
Bjorn Andersson
d65d005f9a clk: qcom: add sc8280xp GCC driver
Add support for the Global Clock Controller found in the Qualcomm
SC8280XP platform.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20220505025457.1693716-3-bjorn.andersson@linaro.org
2022-05-19 16:41:32 -05:00
Adam Skladowski
cadf16c946 clk: qcom: gcc-msm8976: Add modem reset
Add modem reset, it will be needed during modem bringup.

Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220426073048.11509-4-a39.skl@gmail.com
2022-05-05 22:22:27 -05:00
Adam Skladowski
24a8ed12aa clk: qcom: gcc-msm8976: Set floor ops for SDCC
Just like in case of other SoCs change SDCC1/SDCC2 ops
to floor to avoid overclocking controller.
This commit only sets SDCC1/SDCC2 which are used for EMMC/SDCARD.
Leave SDCC3 because on this platform it's mostly used for WIFI/BT chips,
like on Sony Loire familly devices.

Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220426073048.11509-2-a39.skl@gmail.com
2022-05-05 22:22:27 -05:00
Adam Skladowski
665ca429bc clk: qcom: smd: Update MSM8976 RPM clocks.
MSM8976 does not have rpm clock named mmssnoc,
instead it's called sysmmnoc, drop define and reuse.
While we are at it add XO clock to list.

Fixes: 7d61e773c3ed ("clk: qcom: smd: Add support for MSM8976 rpm clocks")
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220426090226.27293-1-a39.skl@gmail.com
2022-04-28 21:42:21 -05:00
Dmitry Baryshkov
d968fda3de clk: qcom: clk-rcg2: fix gfx3d frequency calculation
Since the commit 948fb0969eae ("clk: Always clamp the rounded rate"),
the clk_core_determine_round_nolock() would clamp the requested rate
between min and max rates from the rate request. Normally these fields
would be filled by clk_core_get_boundaries() called from
clk_round_rate().

However clk_gfx3d_determine_rate() uses a manually crafted rate request,
which did not have these fields filled. Thus the requested frequency
would be clamped to 0, resulting in weird frequencies being requested
from the hardware.

Fix this by filling min_rate and max_rate to the values valid for the
respective PLLs (0 and ULONG_MAX).

Fixes: 948fb0969eae ("clk: Always clamp the rounded rate")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220419235447.1586192-1-dmitry.baryshkov@linaro.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reported-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-04-21 19:49:19 -07:00
Michael Srba
5ef1e4abc7 clk: qcom: gcc-msm8998: add SSC-related clocks
Add four clocks which need to be manipulated in order to initialize the AHB
bus which exposes the SCC block in the global address space.

If a device is known to be configured such that writing to these
registers from Linux is not permitted, the 'protected-clocks'
device tree property must be used to denote that fact.

Signed-off-by: Michael Srba <Michael.Srba@seznam.cz>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220411072156.24451-3-michael.srba@seznam.cz
2022-04-19 12:05:14 -05:00
Taniya Das
a9dd26639d clk: qcom: lpass: Add support for LPASS clock controller for SC7280
The Low Power Audio subsystem core and audio clocks are required for
Audio client to be able to request for the clocks and power domains.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220223172248.18877-2-tdas@codeaurora.org
2022-04-12 21:17:42 -05:00
Dmitry Baryshkov
a9ed9e2bf7 clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks
Use newly defined clk_regmap_mux_safe_ops for PCIe pipe clocks to let
the clock framework automatically park the clock when the clock is
switched off and restore the parent when the clock is switched on.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220323085010.1753493-4-dmitry.baryshkov@linaro.org
2022-04-12 13:32:58 -05:00
Dmitry Baryshkov
fa5ad5c517 clk: qcom: gcc-sm8450: use new clk_regmap_mux_safe_ops for PCIe pipe clocks
Use newly defined clk_regmap_mux_safe_ops for PCIe pipe clocks to let
the clock framework automatically park the clock when the clock is
switched off and restore the parent when the clock is switched on.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220323085010.1753493-3-dmitry.baryshkov@linaro.org
2022-04-12 13:32:56 -05:00
Dmitry Baryshkov
e9a4c7f667 clk: qcom: regmap-mux: add pipe clk implementation
On recent Qualcomm platforms the QMP PIPE clocks feed into a set of
muxes which must be parked to the "safe" source (bi_tcxo) when
corresponding GDSC is turned off and on again. Currently this is
handcoded in the PCIe driver by reparenting the gcc_pipe_N_clk_src
clock. However the same code sequence should be applied in the
pcie-qcom endpoint, USB3 and UFS drivers.

Rather than copying this sequence over and over again, follow the
example of clk_rcg2_shared_ops and implement this parking in the
enable() and disable() clock operations. As we are changing the parent
behind the back of the clock framework, also implement custom
set_parent() and get_parent() operations behaving accroding to the clock
framework expectations (cache the new parent if the clock is in disabled
state, return cached parent).

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220323085010.1753493-2-dmitry.baryshkov@linaro.org
2022-04-12 13:32:53 -05:00
Linus Torvalds
9512433987 There's one large change in the core clk framework here. We change how
clk_set_rate_range() works so that the frequency is re-evaulated each time the
 rate is changed. Previously we wouldn't let clk providers see a rate that was
 different if it was still within the range, which could be bad for power if the
 clk could run slower when a range expands. Now the clk provider can decide to
 do something differently when the constraints change. This broke Nvidia's clk
 driver so we had to wait for the fix for that to bake a little more in -next.
 
 The rate range patch series also introduced a kunit suite for the clk framework
 that we're going to extend in the next release. It already made it easy to find
 corner cases in the rate range patches so I'm excited to see it cover more clk
 code and increase our confidence in core framework patches in the future. I
 also added a kunit test for the basic clk gate code and that work will continue
 to cover more basic clk types: muxes, dividers, etc.
 
 Beyond the core code we have the usual set of clk driver updates and additions.
 Qualcomm again dominates the diffstat here with lots more SoCs being supported
 and i.MX follows afer that with a similar number of SoCs gaining clk drivers.
 Beyond those large additions there's drivers being modernized to use
 clk_parent_data so we can move away from global string names for all the clks
 in an SoC. Finally there's lots of little fixes all over the clk drivers for
 typos, warnings, and missing clks that aren't critical and get batched up
 waiting for the next merge window to open. Nothing super big stands out in the
 driver pile. Full details are below.
 
 Core:
  - Make clk_set_rate_range() re-evaluate the limits each time
  - Introduce various clk_set_rate_range() tests
  - Add clk_drop_range() to drop a previously set range
 
 New Drivers:
  - i.MXRT1050 clock driver and bindings
  - i.MX8DXL clock driver and bindings
  - i.MX93 clock driver and bindings
  - NCO blocks on Apple SoCs
  - Audio clks on StarFive JH7100 RISC-V SoC
  - Add support for the new Renesas RZ/V2L SoC
  - Qualcomm SDX65 A7 PLL
  - Qualcomm SM6350 GPU clks
  - Qualcomm SM6125, SM6350, QCS2290 display clks
  - Qualcomm MSM8226 multimedia clks
 
 Updates:
  - Kunit tests for clk-gate implementation
  - Terminate arrays with sentinels and make that clearer
  - Cleanup SPDX tags
  - Fix typos in comments
  - Mark mux table as const in clk-mux
  - Make the all_lists array const
  - Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding and add
    support for dynamic mode
  - Clock configuration on Microchip PolarFire SoCs
  - Free allocations on probe error in Mediatek clk driver
  - Modernize Mediatek clk driver by consolidating code
  - Add watchdog (WDT), I2C, and pin function controller (PFC) clocks on
    Renesas R-Car S4-8
  - Improve the clocks for the Rockchip rk3568 display outputs (parenting, pll-rates)
  - Use of_device_get_match_data() instead of open-coding on Rockchip rk3568
  - Reintroduce the expected fractional-divider behaviour that disappeared
    with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS
  - Remove SYS PLL 1/2 clock gates for i.MX8M*
  - Remove AUDIO MCLK ROOT from i.MX7D
  - Add fracn gppll clock type used by i.MX93
  - Add new composite clock for i.MX93
  - Add missing media mipi phy ref clock for i.MX8MP
  - Fix off by one in imx_lpcg_parse_clks_from_dt()
  - Rework for the imx pll14xx
  - sama7g5: One low priority fix for GCLK of PDMC
  - Add DMA engine (SYS-DMAC) clocks on Renesas R-Car S4-8
  - Add MOST (MediaLB I/F) clocks on Renesas R-Car E3 and D3
  - Add CAN-FD clocks on Renesas R-Car V3U
  - Qualcomm SC8280XP RPMCC
  - Add some missing clks on Qualcomm MSM8992/MSM8994/MSM8998 SoCs
  - Rework Qualcomm GCC bindings and convert SDM845 camera bindig to YAML
  - Convert various Qualcomm drivers to use clk_parent_data
  - Remove test clocks from various Qualcomm drivers
  - Crypto engine clks on Qualcomm IPQ806x + more freqs for SDCC/NSS
  - Qualcomm SM8150 EMAC, PCIe, UFS GDSCs
  - Better pixel clk frequency support on Qualcomm RCG2 clks
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "There's one large change in the core clk framework here. We change how
  clk_set_rate_range() works so that the frequency is re-evaulated each
  time the rate is changed. Previously we wouldn't let clk providers see
  a rate that was different if it was still within the range, which
  could be bad for power if the clk could run slower when a range
  expands. Now the clk provider can decide to do something differently
  when the constraints change. This broke Nvidia's clk driver so we had
  to wait for the fix for that to bake a little more in -next.

  The rate range patch series also introduced a kunit suite for the clk
  framework that we're going to extend in the next release. It already
  made it easy to find corner cases in the rate range patches so I'm
  excited to see it cover more clk code and increase our confidence in
  core framework patches in the future. I also added a kunit test for
  the basic clk gate code and that work will continue to cover more
  basic clk types: muxes, dividers, etc.

  Beyond the core code we have the usual set of clk driver updates and
  additions. Qualcomm again dominates the diffstat here with lots more
  SoCs being supported and i.MX follows afer that with a similar number
  of SoCs gaining clk drivers. Beyond those large additions there's
  drivers being modernized to use clk_parent_data so we can move away
  from global string names for all the clks in an SoC. Finally there's
  lots of little fixes all over the clk drivers for typos, warnings, and
  missing clks that aren't critical and get batched up waiting for the
  next merge window to open. Nothing super big stands out in the driver
  pile. Full details are below.

  Core:
   - Make clk_set_rate_range() re-evaluate the limits each time
   - Introduce various clk_set_rate_range() tests
   - Add clk_drop_range() to drop a previously set range

  New Drivers:
   - i.MXRT1050 clock driver and bindings
   - i.MX8DXL clock driver and bindings
   - i.MX93 clock driver and bindings
   - NCO blocks on Apple SoCs
   - Audio clks on StarFive JH7100 RISC-V SoC
   - Add support for the new Renesas RZ/V2L SoC
   - Qualcomm SDX65 A7 PLL
   - Qualcomm SM6350 GPU clks
   - Qualcomm SM6125, SM6350, QCS2290 display clks
   - Qualcomm MSM8226 multimedia clks

  Updates:
   - Kunit tests for clk-gate implementation
   - Terminate arrays with sentinels and make that clearer
   - Cleanup SPDX tags
   - Fix typos in comments
   - Mark mux table as const in clk-mux
   - Make the all_lists array const
   - Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding
     and add support for dynamic mode
   - Clock configuration on Microchip PolarFire SoCs
   - Free allocations on probe error in Mediatek clk driver
   - Modernize Mediatek clk driver by consolidating code
   - Add watchdog (WDT), I2C, and pin function controller (PFC) clocks
     on Renesas R-Car S4-8
   - Improve the clocks for the Rockchip rk3568 display outputs
     (parenting, pll-rates)
   - Use of_device_get_match_data() instead of open-coding on Rockchip
     rk3568
   - Reintroduce the expected fractional-divider behaviour that
     disappeared with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS
   - Remove SYS PLL 1/2 clock gates for i.MX8M*
   - Remove AUDIO MCLK ROOT from i.MX7D
   - Add fracn gppll clock type used by i.MX93
   - Add new composite clock for i.MX93
   - Add missing media mipi phy ref clock for i.MX8MP
   - Fix off by one in imx_lpcg_parse_clks_from_dt()
   - Rework for the imx pll14xx
   - sama7g5: One low priority fix for GCLK of PDMC
   - Add DMA engine (SYS-DMAC) clocks on Renesas R-Car S4-8
   - Add MOST (MediaLB I/F) clocks on Renesas R-Car E3 and D3
   - Add CAN-FD clocks on Renesas R-Car V3U
   - Qualcomm SC8280XP RPMCC
   - Add some missing clks on Qualcomm MSM8992/MSM8994/MSM8998 SoCs
   - Rework Qualcomm GCC bindings and convert SDM845 camera bindig to
     YAML
   - Convert various Qualcomm drivers to use clk_parent_data
   - Remove test clocks from various Qualcomm drivers
   - Crypto engine clks on Qualcomm IPQ806x + more freqs for SDCC/NSS
   - Qualcomm SM8150 EMAC, PCIe, UFS GDSCs
   - Better pixel clk frequency support on Qualcomm RCG2 clks"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (227 commits)
  clk: zynq: Update the parameters to zynq_clk_register_periph_clk
  clk: zynq: trivial warning fix
  clk: Drop the rate range on clk_put()
  clk: test: Test clk_set_rate_range on orphan mux
  clk: Initialize orphan req_rate
  dt-bindings: clock: drop useless consumer example
  dt-bindings: clock: renesas: Make example 'clocks' parsable
  clk: qcom: gcc-msm8994: Fix gpll4 width
  dt-bindings: clock: fix dt_binding_check error for qcom,gcc-other.yaml
  clk: rs9: Add Renesas 9-series PCIe clock generator driver
  clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index()
  clk: visconti: prevent array overflow in visconti_clk_register_gates()
  dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator
  clk: sifive: Move all stuff into SoCs header files from C files
  clk: sifive: Add SoCs prefix in each SoCs-dependent data
  riscv: dts: Change the macro name of prci in each device node
  dt-bindings: change the macro name of prci in header files and example
  clk: sifive: duplicate the macro definitions for the time being
  clk: qcom: sm6125-gcc: fix typos in comments
  clk: ti: clkctrl: fix typos in comments
  ...
2022-03-30 10:11:04 -07:00
Stephen Boyd
c64dd8ea8e Merge branches 'clk-range', 'clk-uniphier', 'clk-apple' and 'clk-qcom' into clk-next
- Make clk_set_rate_range() re-evaluate the limits each time
 - Introduce various clk_set_rate_range() tests
 - Add clk_drop_range() to drop a previously set range
 - Support for NCO blocks on Apple SoCs

* clk-range:
  clk: Drop the rate range on clk_put()
  clk: test: Test clk_set_rate_range on orphan mux
  clk: Initialize orphan req_rate
  clk: bcm: rpi: Run some clocks at the minimum rate allowed
  clk: bcm: rpi: Set a default minimum rate
  clk: bcm: rpi: Add variant structure
  clk: Add clk_drop_range
  clk: Always set the rate on clk_set_range_rate
  clk: Use clamp instead of open-coding our own
  clk: Always clamp the rounded rate
  clk: Enforce that disjoints limits are invalid
  clk: Introduce Kunit Tests for the framework
  clk: Fix clk_hw_get_clk() when dev is NULL

* clk-uniphier:
  clk: uniphier: Fix fixed-rate initialization

* clk-apple:
  clk: clk-apple-nco: Allow and fix module building
  MAINTAINERS: Add clk-apple-nco under ARM/APPLE MACHINE
  clk: clk-apple-nco: Add driver for Apple NCO
  dt-bindings: clock: Add Apple NCO

* clk-qcom: (61 commits)
  clk: qcom: gcc-msm8994: Fix gpll4 width
  dt-bindings: clock: fix dt_binding_check error for qcom,gcc-other.yaml
  clk: qcom: Add display clock controller driver for SM6125
  dt-bindings: clock: add QCOM SM6125 display clock bindings
  clk: qcom: Fix sorting of SDX_GCC_65 in Makefile and Kconfig
  clk: qcom: gcc: Add emac GDSC support for SM8150
  clk: qcom: gcc: sm8150: Fix some identation issues
  clk: qcom: gcc: Add UFS_CARD and UFS_PHY GDSCs for SM8150
  clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150
  clk: qcom: clk-rcg2: Update the frac table for pixel clock
  clk: qcom: clk-rcg2: Update logic to calculate D value for RCG
  clk: qcom: smd: Add missing MSM8998 RPM clocks
  clk: qcom: smd: Add missing RPM clocks for msm8992/4
  dt-bindings: clock: qcom: rpmcc: Add RPM Modem SubSystem (MSS) clocks
  clk: qcom: gcc-ipq806x: add CryptoEngine resets
  dt-bindings: reset: add ipq8064 ce5 resets
  clk: qcom: gcc-ipq806x: add CryptoEngine clocks
  dt-bindings: clock: add ipq8064 ce5 clk define
  clk: qcom: gcc-ipq806x: add additional freq for sdc table
  clk: qcom: clk-rcg: add clk_rcg_floor_ops ops
  ...
2022-03-29 10:19:36 -07:00
Stephen Boyd
4222744d40 Merge branches 'clk-starfive', 'clk-ti', 'clk-terminate' and 'clk-cleanup' into clk-next
- Audio clks on StarFive JH7100 RISC-V SoC
 - Terminate arrays with sentinels and make that clearer
 - Cleanup SPDX tags
 - Fix typos in comments

* clk-starfive:
  clk: starfive: Add JH7100 audio clock driver
  clk: starfive: jh7100: Support more clock types
  clk: starfive: jh7100: Make hw clock implementation reusable
  dt-bindings: clock: Add starfive,jh7100-audclk bindings
  dt-bindings: clock: Add JH7100 audio clock definitions
  clk: starfive: jh7100: Handle audio_div clock properly
  clk: starfive: jh7100: Don't round divisor up twice

* clk-ti:
  clk: ti: Drop legacy compatibility clocks for dra7
  clk: ti: Drop legacy compatibility clocks for am4
  clk: ti: Drop legacy compatibility clocks for am3
  clk: ti: Update component clocks to use ti_dt_clk_name()
  clk: ti: Update pll and clockdomain clocks to use ti_dt_clk_name()
  clk: ti: Add ti_dt_clk_name() helper to use clock-output-names
  clk: ti: Use clock-output-names for clkctrl
  clk: ti: Add ti_find_clock_provider() to use clock-output-names
  clk: ti: Optionally parse IO address from parent clock node
  clk: ti: Preserve node in ti_dt_clocks_register()
  clk: ti: Constify clkctrl_name

* clk-terminate:
  clk: actions: Make sentinel elements more obvious
  clk: clps711x: Terminate clk_div_table with sentinel element
  clk: hisilicon: Terminate clk_div_table with sentinel element
  clk: loongson1: Terminate clk_div_table with sentinel element
  clk: actions: Terminate clk_div_table with sentinel element

* clk-cleanup:
  clk: zynq: Update the parameters to zynq_clk_register_periph_clk
  clk: zynq: trivial warning fix
  clk: qcom: sm6125-gcc: fix typos in comments
  clk: ti: clkctrl: fix typos in comments
  clk: COMMON_CLK_LAN966X should depend on SOC_LAN966
  clk: Use of_device_get_match_data()
  clk: bcm2835: Remove unused variable
  clk: tegra: tegra124-emc: Fix missing put_device() call in emc_ensure_emc_driver
  clk: cleanup comments
  clk: socfpga: cleanup spdx tags
2022-03-29 10:19:10 -07:00
Konrad Dybcio
71021db1c5 clk: qcom: gcc-msm8994: Fix gpll4 width
The gpll4 postdiv is actually a div4, so make sure that Linux is aware of
this.

This fixes the following error messages:

 mmc1: Card appears overclocked; req 200000000 Hz, actual 343999999 Hz
 mmc1: Card appears overclocked; req 400000000 Hz, actual 687999999 Hz

Fixes: aec89f78cf01 ("clk: qcom: Add support for msm8994 global clock controller")
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20220319174940.341137-1-konrad.dybcio@somainline.org
Tested-by: Petr Vorel <petr.vorel@gmail.com>
Reviewed-by: Petr Vorel <petr.vorel@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-03-24 17:52:51 -07:00
Julia Lawall
bb7f4b8c1e clk: qcom: sm6125-gcc: fix typos in comments
Various spelling mistakes in comments.
Detected with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Link: https://lore.kernel.org/r/20220314115354.144023-16-Julia.Lawall@inria.fr
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-03-15 15:48:38 -07:00
Martin Botka
6e87c8f074 clk: qcom: Add display clock controller driver for SM6125
Add support for the display clock controller found on SM6125
based devices. This allows display drivers to probe and
control their clocks.

Signed-off-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220303131812.302302-4-marijn.suijten@somainline.org
2022-03-09 08:53:30 -06:00