3 Commits

Author	SHA1	Message	Date
Will Deacon	c739dc83a0	arm64: lse: rename ARM64_CPU_FEAT_LSE_ATOMICS for consistency ... Other CPU features follow an 'ARM64_HAS_*' naming scheme, so do the same for the LSE atomics. Signed-off-by: Will Deacon <will.deacon@arm.com>	2015-07-27 15:28:54 +01:00
Will Deacon	084f903727	arm64: bitops: patch in lse instructions when supported by the CPU ... On CPUs which support the LSE atomic instructions introduced in ARMv8.1, it makes sense to use them in preference to ll/sc sequences. This patch introduces runtime patching of our bitops functions so that LSE atomic instructions are used instead. Reviewed-by: Steve Capper <steve.capper@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>	2015-07-27 15:28:51 +01:00
Will Deacon	c09d6a04d1	arm64: atomics: patch in lse instructions when supported by the CPU ... On CPUs which support the LSE atomic instructions introduced in ARMv8.1, it makes sense to use them in preference to ll/sc sequences. This patch introduces runtime patching of atomic_t and atomic64_t routines so that the call-site for the out-of-line ll/sc sequences is patched with an LSE atomic instruction when we detect that the CPU supports it. If binutils is not recent enough to assemble the LSE instructions, then the ll/sc sequences are inlined as though CONFIG_ARM64_LSE_ATOMICS=n. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>	2015-07-27 15:28:50 +01:00