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The new reset controller API is optional, so if that is disabled,
we must not call it from platform code.
arch/arm/mach-imx/built-in.o: In function
`imx_src_init': /git/arm-soc/arch/arm/mach-imx/src.c:144:
undefined reference to `reset_controller_register'
Cc: Sascha Hauer <kernel@pengutronix.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Enable anatop, well bisa and RBC for suspend to optimize the power
consumption a little bit
* Clock changes for TVE, LDB, PATA, SRTC support
* Add System Reset Controller (SRC) support for imx5 and imx6
* Add initial imx6dl support based on imx6q code
* Kconfig for cpufreq-cpu0, defconfig updates and few other changes
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Merge tag 'imx-soc-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc2
From Shawn Guo:
The imx soc changes for 3.10:
* Enable anatop, well bisa and RBC for suspend to optimize the power
consumption a little bit
* Clock changes for TVE, LDB, PATA, SRTC support
* Add System Reset Controller (SRC) support for imx5 and imx6
* Add initial imx6dl support based on imx6q code
* Kconfig for cpufreq-cpu0, defconfig updates and few other changes
* tag 'imx-soc-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6: (275 commits)
ARM i.MX53: set CLK_SET_RATE_PARENT flag on the tve_ext_sel clock
ARM i.MX53: tve_di clock is not part of the CCM, but of TVE
ARM i.MX53: make tve_ext_sel propagate rate change to PLL
ARM i.MX53: Remove unused tve_gate clkdev entry
ARM i.MX5: Remove tve_sel clock from i.MX53 clock tree
ARM: i.MX5: Add PATA and SRTC clocks
ARM: imx: do not bring up unavailable cores
ARM: imx: add initial imx6dl support
ARM: imx1: mm: add call to mxc_device_init
ARM: imx_v4_v5_defconfig: Add CONFIG_GPIO_SYSFS
ARM: imx_v6_v7_defconfig: Select CONFIG_PERF_EVENTS
ARM: i.MX53 Add the cko1, cko2 clock outputs.
staging: drm/imx: Use SRC to reset IPU
ARM i.MX6q: Add GPU, VPU, IPU, and OpenVG resets to System Reset Controller (SRC)
ARM: imx: do not use regmap_read for ANADIG_DIGPROG
ARM i.MX6q: set the LDB serial clock parent to the video PLL
ARM i.MX6q: Add audio/video PLL post dividers for i.MX6q rev 1.1
ARM i.MX6q: fix ldb di divider and selector clocks
ARM i.MX53: fix ldb di divider and selector clocks
ARM i.MX: Add imx_clk_divider_flags and imx_clk_mux_flags
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Trivial change/change conflict in arch/arm/mach-imx/mach-imx6q.c resolved.
Use imx_clk_mux_flags to set the appropriate flags for the TVE
selector clock. This is needed so tve_clk rate changes can propagate
up to pll4_sw.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Remove the tve_di clock from the CCM clock tree. It will be provided
by the Television Encoder driver, as this clock is an output signal
of the TVE module.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This is needed so the Television Encoder driver can set the rate
on tve_clk and have it propagated up to pll4_sw.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This adds the clock gates and the binding documentation
for PATA and SRTC.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The i.MX6 Quad can be fused as i.MX6 Dual chip, and similarly i.MX6
DualLite can be fused as i.MX6 Solo. The actual number of available
cores can be found out from SCU.
Since we do not reflect the fusing thing in device tree, the function
arm_dt_init_cpu_maps() will always call set_cpu_possible(true) for 4
cores on i.MX6 Quad/Dual and 2 cores for i.MX6 DualLite/Solo. This
causes failures when kernel tries to bring those unavailable cores
online. For example, the following failure message will be seen when
booting an i.MX6 Solo chip.
CPU1: failed to come online
Though kernel will still boot fine, the message is somehow annoying.
Let's get rid of it by calling set_cpu_possible(false) on those
unavailable cores.
While at it, the set_cpu_possible(true) for available cores is removed,
since it's already been done in arm_dt_init_cpu_maps().
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The i.MX6 DualLite/Solo is another i.MX6 family SoC, which is highly
compatible with i.MX6 Quad/Dual. And that's why we choose to support
it using imx6q code with cpu_is_imx6dl() check when necessary.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
mxc_device_init() is mandatory for mxc_aips and mxc_ahb bus registration, needed
as parents, at least, for gpio and dma.
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
These two clocks connect to external pins and can be muxed to
various internal clocks.
They are typically used either for debugging or to provide
clocks to external chips (eg audio codecs).
Currently only the selectable clocks that already exist in the clock tree
have been added.
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The SRC has auto-deasserting reset bits that control reset lines to
the GPU, VPU, IPU, and OpenVG IP modules. This patch adds a reset
controller that can be controlled by those devices using the
reset controller API.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Function imx_anatop_get_digprog() that reads register ANADIG_DIGPROG is
called to identify silicon version. Users might query silicon version
earlier than regmap subsystem is ready. For example, imx6q clock driver
query revision in mx6q_clocks_init(), where regmap is not initialized
yet.
Change imx_anatop_get_digprog() to map anatop block and read
ANADIG_DIGPROG in the native way, so that the function can work at very
early stage.
While at it, let's move imx_print_silicon_rev() back to
imx6q_timer_init() to have the message show up a little earlier.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
On i.MX6q revision 1.1 and later, set the video PLL as parent for
the LDB clock branch. On revision 1.0, the video PLL is useless
due to missing dividers, so keep the default parent (mmdc_ch1_axi).
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Query silicon revision to determine clock tree and add post
dividers for newer revisions.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Use imx_clk_mux_flags and imx_clk_divider_flags to set the appropriate
flags for the LDB display interface divider and selector clocks.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Use imx_clk_mux_flags and imx_clk_divider_flags to set the appropriate
flags for the LDB display interface divider and selector clocks.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The default is for dividers to set CLK_SET_PARENT_RATE and for muxes to
not set that flag. In the LDB clock tree, we need the opposite, so add
functions to create divider and mux clocks with configurable flags.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
So it can be used in clk-imx6q.c for revision dependent clock tree setup.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
There are some config options not selected by imx27 and imx5 that are
necessary to use the cpufreq-cpu0 driver.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch adds the missing GPU2D and GPU3D mux and gate clocks,
and the graphics arbiter gate clock.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Fix the following sparse warnings:
arch/arm/mach-imx/anatop.c:56:6: warning: symbol 'imx_anatop_pre_suspend' was not declared. Should it be static?
arch/arm/mach-imx/anatop.c:62:6: warning: symbol 'imx_anatop_post_resume' was not declared. Should it be static?
arch/arm/mach-imx/anatop.c:68:6: warning: symbol 'imx_anatop_usb_chrg_detect_disable' was not declared. Should it be static?
arch/arm/mach-imx/anatop.c:78:5: warning: symbol 'imx_anatop_get_digprog' was not declared. Should it be static?
arch/arm/mach-imx/anatop.c:86:13: warning: symbol 'imx_anatop_init' was not declared. Should it be static?
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
RBC is to control whether some ANATOP sub modules
can enter lpm mode when SOC is into STOP mode, if
RBC is enabled and PMIC_VSTBY_REQ is set, ANATOP
will have below behaviors:
1. Digital LDOs(CORE, SOC and PU) are bypassed;
2. Analog LDOs(1P1, 2P5, 3P0) are disabled;
As the 2P5 is necessary for DRAM IO pre-drive in
STOP mode, so we need to enable weak 2P5 in STOP
mode when 2P5 LDO is disabled.
For RBC settings, there are some rules as below
due to hardware design:
1. All interrupts must be masked during operating
RBC registers;
2. At least 2 CKIL(32K) cycles is needed after the
RBC setting is changed.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Anatop module have sereval configurations for user
to reduce the power consumption in suspend, provide
suspend/resume interface for further use and enable
fet_odrive to reduce CORE LDO leakage during suspend.
As we have a common anatop file, remove all the operations
of anatop module in other files, use anatop interfaces to
do that.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* Clean up a couple of unneeded function declarations
* Remove imx specific cpufreq driver as generic cpufreq-cpu0 works well
as the replacement
* Remove platform ahci support
* Clean up unused ARCH/MACH Kconfig symbols
* Remove a couple of unused files
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Merge tag 'imx-cleanup-3.10' into imx/soc
The imx cleanup for 3.10:
* Clean up a couple of unneeded function declarations
* Remove imx specific cpufreq driver as generic cpufreq-cpu0 works well
as the replacement
* Remove platform ahci support
* Clean up unused ARCH/MACH Kconfig symbols
* Remove a couple of unused files
The i.MX53 ahci platform support is unused in mainline. To demotivate
people using it just remove it from the tree.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
According to the recent i.MX6 Quad technical reference manual, mode 0x4 (100b)
of the CCM_CS2DCR register (address 0x020C402C) bits [11-9] and [14-12] select
the PLL3 clock, and not the PLL3 PFD1 540M clock. In our code, the PLL3 root
clock is named 'pll3_usb_otg', select this instead of the 540M clock.
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
While booting from device tree, imx6q used to provide twd clock lookup
by calling clk_register_clkdev() in clock driver. However, the commit
bd60345 (ARM: use device tree to get smp_twd clock) forces DT boot to
look up the clock from device tree. It causes the failure below when
twd driver tries to get the clock, and hence kernel has to calibrate the
local timer frequency.
smp_twd: clock not found -2
...
Calibrating local timer... 396.13MHz.
Fix the regression by providing twd clock lookup from device tree, and
remove the unused twd clk_register_clkdev() call from clock driver.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The admux clock seems to be the audmux clock as tests show. audmux does
not work without this clock enabled. Currently imx35 does not register a
clock device for audmux. This patch adds this registration. imx-audmux
driver already handles a clock device, so no changes are necessary
there.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Cc: stable@vger.kernel.org
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch enables iomuxc_gate clock. It is necessary to be able to
reconfigure iomux pads. Without this clock enabled, the
clk_disable_unused function will disable this clock and the iomux pads
are not configurable anymore. This happens at every boot. After a reboot
(watchdog system reset) the clock is not enabled again, so all iomux pad
reconfigurations in boot code are without effect.
The iomux pads should be always configurable, so this patch always
enables it.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Cc: stable@vger.kernel.org
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Both zynq and shmobile have conflicts against the gic cleanup
series, resolved here.
Conflicts:
arch/arm/mach-shmobile/smp-emev2.c
arch/arm/mach-shmobile/smp-r8a7779.c
arch/arm/mach-shmobile/smp-sh73a0.c
arch/arm/mach-zynq/platsmp.c
drivers/gpio/gpio-pl061.c
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
From Michal Simek <michal.simek@xilinx.com>:
This branch is based on zynq/clksrc/cleanup parts because
there are some dependencies on moving timer to generic location.
I could based it on standard Linux tagged version but you will get
several conflicts you will have to resolve.
If you are OK to resolving these problems, please let me know
I will create another branch with core-smp changes which are not based
on zynq/clksrc/cleanup branch.
* 'zynq/core-smp' of git://git.xilinx.com/linux-xlnx:
arm: zynq: Add hotplug support
arm: zynq: Add smp support
arm: zynq: Add smp_twd timer
arm: zynq: Get rid of xilinx function prefix
arm: zynq: Add support for system reset
arm: zynq: Move slcr initialization to separate file
arm: zynq: Load scu baseaddress at run time
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
imx ssi block has two types of clocks:
- ipg: bus clock, the clock needed for accessing registers.
- per: peripheral clock, the clock needed for generating the bit rate.
Currently ssi driver only supports slave mode and thus need only to handle
the ipg clock, because the peripheral clock comes from the master codec.
Only register the ipg clock and do not register the peripheral clock for ssi
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
When building a kernel with CONFIG_PM undefined, the following warning happens:
arch/arm/mach-imx/avic.c:57:12: warning: 'avic_saved_mask_reg' defined but not used [-Wunused-variable]
Move avic_saved_mask_reg definition inside the '#ifdef CONFIG_PM' block to
avoid the warning.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The old cpufreq driver is not necessary anymore with DT and
cpufreq-cpu0.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Commit a1f1c7e (arm/imx6q: add suspend/resume support) added
declaration for a non-existing function pl310_get_save_ptr() by
mistake. Remove it.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Running suspend/resume without no_console_suspend setting on kernel
cmdline will likely makes system hang. It causesd by the sync issue
between imx_cpu_die() and imx_cpu_kill() call. Fix the issue by
synchronizing the calls using cpu jumping argument register which is
free to use in kernel.
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Merge tag 'imx-fixes-3.9-4' of git://git.linaro.org/people/shawnguo/linux-2.6 into fixes
From Shawn Guo <shawn.guo@linaro.org>:
The imx fixes for 3.9, take 4:
Running suspend/resume without no_console_suspend setting on kernel
cmdline will likely makes system hang. It causesd by the sync issue
between imx_cpu_die() and imx_cpu_kill() call. Fix the issue by
synchronizing the calls using cpu jumping argument register which is
free to use in kernel.
* tag 'imx-fixes-3.9-4' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: imx: fix sync issue between imx_cpu_die and imx_cpu_kill
ARM: imx: add dependency check for DEBUG_IMX_UART_PORT
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
All the calls to gic_secondary_init() pass 0 as the first argument.
Since this function is called on each CPU when starting, it can be done
in a platform-independent way via a CPU notifier registered by the GIC
code.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Tested-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Barry Song <baohua.song@csr.com>
There is a sync issue with hotplug operation. It's possible that when
imx_cpu_kill gets running on primary core, the imx_cpu_die execution
on the core which is to be killed hasn't been finished yet. The problem
will very likely be hit when running suspend without no_console_suspend
setting on kernel cmdline.
It uses cpu jumping argument register to sync imx_cpu_die and
imx_cpu_kill. The register will be set in imx_cpu_die and imx_cpu_kill
will wait for the register being cleared to actually kill the cpu.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: <stable@vger.kernel.org>
The i.MX35 has two bits per clock gate which are decoded as follows:
0b00 -> clock off
0b01 -> clock is on in run mode, off in wait/doze
0b10 -> clock is on in run/wait mode, off in doze
0b11 -> clock is always on
The reset value for the MAX clock is 0b10.
The MAX clock is needed by the SoC, yet unused in the Kernel, so the
common clock framework will disable it during late init time. It will
only disable clocks though which it detects as being turned on. This
detection is made depending on the lower bit of the gate. If the reset
value has been altered by the bootloader to 0b11 the clock framework
will detect the clock as turned on, yet unused, hence it will turn it
off and the system locks up.
This patch turns the MAX clock on unconditionally making the Kernel
independent of the bootloader.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The i.MX25 DT machine descriptor calls a non existing imx25_timer_init()
function. This patch adds it to fix compilation.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Now that we have OF based init with CLKSRC_OF, convert smp_twd init
function to use it and covert all callers of
twd_local_timer_of_register.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: John Stultz <johnstul@us.ibm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-omap@vger.kernel.org
Cc: spear-devel@list.st.com
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
We always boot from PLL1, so let's have pll1_sys in the clks_init_on
list to have clk prepare/enable use count match the hardware status,
so that drivers managing pll1_sys like cpufreq can get the use count
right from the start.
Reported-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
