5074 Commits

Author SHA1 Message Date
Jerome Brunet
80d396b511 clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition
HHI_GEN_CLK_CTNL is defined twice, just remove the duplicate definition

Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver")
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09 13:49:22 +02:00
Yixun Lan
cddcb20b2b clk: meson-axg: add clocks required by pcie driver
Adding clocks for the pcie driver. Due to the ASIC design,
the pcie controller re-use part of the mipi clock logic,
so the mipi clock is also added.

Tested-by: Jianxin Qin <jianxin.qin@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
[amended to remove unnecessary locales]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09 13:49:11 +02:00
Jerome Brunet
85ddc1a32c clk: meson: remove unused clk-audio-divider driver
clk-audio-divider is no longer used, we can remove it.

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09 13:48:59 +02:00
Jerome Brunet
9799d5ae00 clk: meson: stop rate propagation for audio clocks
It is actually a lot easier to setup the PLL with carefully chosen rates
than relying on CCF clock propagation for this audio use case.
This way, we can make sure we will always be able to provide the common
audio clock rates, while having the PLL in the optimal operating range.

For this, we stop the rate propagation at the mux picking the
PLL and let it round to the closest matching PLL.

Doing so, we can use the generic divider for the i2s clock.
clk-audio-divider is no longer required. It was a (poor) attempt
to use CCF rate propagation while making sure the PLL rate would
be high enough to work with audio use cases.

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09 13:48:59 +02:00
Jerome Brunet
1cd5018175 clk: meson: axg: add the audio clock controller driver
The axg audio clock controller is the clock generation unit for the
amlogic audio subsystem of A113 based SoCs. It may be clocked by 8
different plls provided by the primary clock controller and also by
10 slave bit clocks and 10 slave sample clocks which may be provided
by external components, such as audio codecs, through the SoC pads.

It contains several muxes, dividers and gates which are fed into the
the different devices of the audio subsystem.

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09 13:48:26 +02:00
Jerome Brunet
3054a55c5d clk: meson: add axg audio sclk divider driver
Add a driver to control the clock divider found in the sample clock
generator of the axg audio clock controller.

The sclk divider accumulates specific features which make the generic
divider unsuitable to control it:
- zero based divider (div = val + 1), but zero value gates the clock,
  so minimum divider value is 2.
- lrclk variant may adjust the duty cycle depending the divider value
  and the 'hi' value.

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09 13:48:25 +02:00
Jerome Brunet
2eb2a01b64 Merge remote-tracking branch 'clk/clk-core-duty-cycle' into next/drivers 2018-07-09 13:47:38 +02:00
Jerome Brunet
e8dd920776 clk: meson: add triple phase clock driver
Add a driver to control the output of the sample clock generator found
in the axg audio clock controller.

The goal of this driver is to coherently control the phase provided to
the different element using the sample clock generator. This simplify
the usage of the sample clock generator a lot, without comprising the
ability of the SoC.

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09 13:47:22 +02:00
Jerome Brunet
47f21315a6 clk: meson: add clk-phase clock driver
Add a driver based meson clk-regmap to control clock phase on
amlogic SoCs

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09 13:47:22 +02:00
Jerome Brunet
443f228578 clk: meson: clean-up meson clock configuration
Clean the dependencies in meson clock Kconfig.
CLK_AMLOGIC should actually select CLK_REGMAP_MESON which it uses. Also,
each platform should select CLK_AMLOGIC, so everything is properly turned
on when the platform Kconfig enable each configuration flag

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09 13:46:21 +02:00
Jerome Brunet
60e267f3fd clk: meson: remove obsolete register access
The legacy method to access the hhi register space is not longer used.
We can safely drop it now.

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09 13:46:21 +02:00
Dmitry Osipenko
405fcacbd8 clk: tegra: emc: Avoid out-of-bounds bug
Apparently there was an attempt to avoid out-of-bounds accesses when there
is only one memory timing available, but there is a typo in the code that
neglects that attempt.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-08 17:10:19 -07:00
Dmitry Osipenko
da0d2239a5 clk: tegra: Mark Memory Controller clock as critical
Memory Controller should be always-on. Currently the sibling EMC clock is
marked as critical, let's mark MC clock too for consistency.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-08 17:08:31 -07:00
Thierry Reding
8097d4c75f clk: tegra: Make vde a child of pll_c3
The current default is to leave the VDE clock's parent at the default,
which is clk_m. However, that is not a configuration that will allow the
VDE to function. Reparent it to pll_c3 instead to make sure the hardware
can actually decode video content.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-08 17:06:48 -07:00
Thierry Reding
26f8590c4a clk: tegra: Make vic03 a child of pll_c3
By default, the vic03 clock is a child of pll_m but that runs at 924 MHz
which is too fast for VIC. Make vic03 a child of pll_c3 by default so it
will run at a supported frequency.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-08 17:03:59 -07:00
Mikko Perttunen
f7b3182232 clk: tegra: bpmp: Don't crash when a clock fails to register
When registering clocks, we just skip any that fail to register
(leaving a NULL hole in the clock table). However, our of_xlate
function still tries to dereference each entry while looking for
the clock with the requested id, causing a crash if any clocks
failed to register. Add a check to of_xlate to skip any NULL
clocks.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-08 16:56:24 -07:00
Alberto Panizzo
a64ad00898 clk: rockchip: fix clk_i2sout parent selection bits on rk3399
Register, shift and mask were wrong according to datasheet.

Fixes: 115510053e5e ("clk: rockchip: add clock controller for the RK3399")
Cc: stable@vger.kernel.org
Signed-off-by: Alberto Panizzo <alberto@amarulasolutions.com>
Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-07-08 00:19:19 +02:00
Taniya Das
da172d2b6b clk: qcom: Move frequency table macro to common file
Frequency table macro is used by multiple clock drivers, move frequency
table macro to common header file.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06 16:45:51 -07:00
Stephen Boyd
d0897bc85c clk: imx51-imx53: Include sizes.h to silence compile errors
This driver uses sizes.h, but relies on it being implicitly included
somewhere else breaking random direct compilation of the file. Include
sizes.h so we can build it those configurations too for better compile
coverage.

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06 14:08:04 -07:00
Fabio Estevam
ed235d5569 clk: imx51-imx53: Annotate critical clocks as CLK_IS_CRITICAL
Instead of explicitly enabling critical clocks via clk_prepare_enable(),
let's use the standard CLK_IS_CRITICAL flag instead, which makes the code
a bit shorter.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06 14:04:35 -07:00
Anson Huang
9d8108f9f3 clk: imx6sll: add GPIO LPCGs
According to Reference Manual Rev.0, 06/2017, there are GPIO LPCGs
defined in CCM CCGRs, add them into clock tree.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06 13:58:20 -07:00
Lei YU
cd88259a72 clk: aspeed: Fix SDCLK name
The SDCLK was named SDCLKCLK, and no one has used this yet.
Fix it.

Signed-off-by: Lei YU <mine260309@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06 13:56:06 -07:00
Robert Jarzmik
fc20654389 clk: pxa: export 32kHz PLL
This clock is especially used by the RTC driver, so export it so that
devicetree users can use it.

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06 13:52:57 -07:00
Joel Stanley
974c7c6d7b clk: aspeed: Mark bclk (PCIe) and dclk (VGA) as critical
This is used by the host to talk to the BMC's PCIe slave device. The BMC
is not involved, but the clock needs to be enabled so the host can use
the device.

Fixes: 15ed8ce5f84e ("clk: aspeed: Register gated clocks")
Cc: stable@vger.kernel.org # 4.15
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Tested-by: Lei YU <mine260309@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06 13:48:07 -07:00
Daniel Mack
33f5104624 clk: Add driver for MAX9485
This patch adds a driver for MAX9485, a programmable audio clock generator.

The device requires a 27.000 MHz clock input. It can provide a gated
buffered output of its input clock and two gated outputs of a PLL that can
generate one out of 16 discrete frequencies. There is only one PLL however,
so the two gated outputs will always have the same frequency but they can
be switched individually.

The driver for this device exposes 4 clocks in total:

- MAX9485_MCLKOUT:      A gated, buffered output of the input clock
- MAX9485_CLKOUT:       A PLL that can be configured to 16 different
			discrete frequencies
- MAX9485_CLKOUT[1,2]:  Two gated outputs for MAX9485_CLKOUT

Some PLL output frequencies can be achieved with different register
settings. The driver will select the one with lowest jitter in such cases.

Signed-off-by: Daniel Mack <daniel@zonque.org>
[sboyd@kernel.org: Use local variable for val in max9485_clkout_recalc_rate()
and shorten line of max9485_of_clk_get()]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06 13:44:06 -07:00
Paul Cercueil
2b555a4b9c clk: ingenic: Add missing flag for UDC clock
The UDC clock of the JZ4740 SoC can be gated, but the data structure
representing it was missing the CGU_CLK_GATE flag to make it work.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06 11:47:28 -07:00
Paul Cercueil
574f4e80d5 clk: ingenic: Fix incorrect data for the i2s clock
The register field for configuring the divider for the i2s clock
occupies the bits [8-0], which means 9 bits and not 8.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06 11:47:27 -07:00
Vivek Gautam
53f3abe97b clk/mmcc-msm8996: Make mmagic_bimc_gdsc ALWAYS_ON
Patch (7705bb7176b9 clk: qcom: mmcc-msm8996: leave all mmagic gdscs
and clocks always enabled") makes all mmgaic gdscs ALWAYS_ON.
The mmagic_bimc_gdsc is also needed to be turned on to get display
working on 8x96.

Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Cc: Rajendra Nayak <rnayak@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: 7705bb7176b9 ("clk: qcom: mmcc-msm8996: leave all mmagic gdscs and clocks always enabled")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06 11:24:17 -07:00
Codrin Ciubotariu
96e4ea8c25 clk: at91: add I2S clock mux driver
This driver is a simple muxing driver that controls the
I2S's clock input by using syscon/regmap to change the parent.
The available inputs can be peripheral clock and generated clock.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
[sboyd@kernel.org: Fix SPDX tag comment style]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06 11:12:20 -07:00
Dinh Nguyen
51b9a379a8 clk: socfpga: stratix10: fix the sdmmc_free_clk mux
The first parent of the sdmmc_free_clk should be the main_sdmmc_clk.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06 11:08:02 -07:00
Dinh Nguyen
2772ffd979 clk: socfpga: stratix10: fix the parents of mpu_free_clk
Add a clock mux that is used as a parent for the mpu_free_clk.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06 11:06:42 -07:00
Stephen Boyd
659e839c3c - fix boot issue with gxbb and gxl platforms
- fix racalculation error in the clk_audio_divider
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Merge tag 'meson-clk-fixes-4.18-1' of https://github.com/BayLibre/clk-meson into clk-fixes

Pull Amlogic clk driver fixes from Jerome Brunet:

These are two simple fixes, yet the first one is quite important as it
solves boots hangs we've been having when FDIV2 gets disabled. This did
not show up before because this particular clock is heavily used and
only gets disabled for a very short period of time before modules (such
as ethernet or emmc) probe.

- fix boot issue with gxbb and gxl platforms
- fix racalculation error in the clk_audio_divider

* tag 'meson-clk-fixes-4.18-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: audio-divider is one based
  clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL
2018-07-06 10:57:45 -07:00
Benjamin Herrenschmidt
edc6f7e9b1 clk: aspeed: Treat a gate in reset as disabled
On some systems, we come out of the bootloader with some
gates set with the clock "enabled" but the reset also
asserted.

Since 8a53fc511c5e "clk: aspeed: Prevent reset if clock is enabled"
we check that enabled bit in aspeed_clk_enabled(), and do
nothing if already set.

This breaks when the above scenario occurs, as the clock
is enabled, but the reset still needs to be lifted.

This patch fixes it by also checking the reset bit (if any)
and treating a gate in "reset" as being disabled.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Fixes: 8a53fc511c5e "clk: aspeed: Prevent reset if clock is enabled"
Cc: Eddie James <eajames@linux.vnet.ibm.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06 10:53:20 -07:00
Geert Uytterhoeven
40dd71c75e clk: Really show symbolic clock flags in debugfs
The last-minute fold-in of the ENTRY() macro did change behavior:
instead of printing the symbolic name (e.g. "CLK_IS_BASIC"), it prints
the expansion of it (e.g. "(1UL << (5))").

Use "#" instead of  __stringify() to fix this.

Fixes: a6059ab98130fb56 ("clk: Show symbolic clock flags in debugfs")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06 10:49:27 -07:00
Vinod Koul
5f75b78d3d clk: qcom: gcc-msm8996: Disable halt check on UFS tx clock
Commit 12d807cd34b8 ("clk: qcom: gcc-msm8996: Disable halt check on UFS
clocks") marked BRANCH_HALT_SKIP for ufs rx clocks, but missed ufs tx
clocks. The result of that is kernel warnings at reboot:

[  105.624283] gcc_ufs_tx_symbol_0_clk status stuck at 'on'
[  105.624311] WARNING: CPU: 1 PID: 1 at drivers/clk/qcom/clk-branch.c:100 clk_branch_toggle+0x190/0x1b0
[  105.633235] Modules linked in:
[  105.645118] CPU: 1 PID: 1 Comm: systemd-shutdow Tainted: G        W         4.18.0-rc2-00002-g2bfbe52a53a3 
[  105.647988] Hardware name: Qualcomm Technologies, Inc. DB820c (DT)
[  105.657966] pstate: 60000085 (nZCv daIf -PAN -UAO)
[  105.664127] pc : clk_branch_toggle+0x190/0x1b0
[  105.668900] lr : clk_branch_toggle+0x190/0x1b0
[  105.673324] sp : ffff00000805bb40
[  105.677751] x29: ffff00000805bb40 x28: 0000000000000000
[  105.681140] x27: ffff8000d947cc60 x26: 0000000000000001
[  105.686520] x25: ffff000008f71900 x24: 0000000000000000
[  105.691816] x23: ffff00000925e338 x22: ffff00000855f8e0
[  105.697114] x21: 0000000000000000 x20: 0000000000000000
[  105.702407] x19: ffff0000091c9000 x18: ffffffffffffffff
[  105.707702] x17: 0000ffffac148c58 x16: ffff000008b82928
[  105.712998] x15: ffff0000091c96c8 x14: ffff0000893817c7
[  105.718293] x13: ffff0000093817d5 x12: ffff0000091c9940
[  105.723587] x11: ffff0000085e3e70 x10: ffff00000805b780
[  105.728884] x9 : ffff00000805bb40 x8 : 7320737574617473
[  105.734179] x7 : 206b6c635f305f6c x6 : 00000000000001e5
[  105.739472] x5 : 0000000000000000 x4 : 0000000000000000
[  105.744769] x3 : ffffffffffffffff x2 : ffff0000091e2658
[  105.750063] x1 : a7c4712dd5e09c00 x0 : 0000000000000000
[  105.755360] Call trace:
[  105.760652]  clk_branch_toggle+0x190/0x1b0
[  105.762824]  clk_branch2_disable+0x18/0x20
[  105.766994]  clk_core_disable+0x58/0xa8
[  105.771069]  clk_core_disable_lock+0x20/0x38
[  105.774803]  clk_disable+0x1c/0x28
[  105.779320]  __ufshcd_setup_clocks+0x298/0x308
[  105.782529]  ufshcd_suspend+0x160/0x308
[  105.786953]  ufshcd_shutdown+0x38/0xa0
[  105.790690]  ufshcd_pltfrm_shutdown+0x10/0x18
[  105.794512]  platform_drv_shutdown+0x20/0x30
[  105.798935]  device_shutdown+0x110/0x1e8
[  105.803278]  kernel_restart_prepare+0x34/0x40
[  105.807181]  kernel_restart+0x14/0x78
[  105.811434]  sys_reboot+0x200/0x248
[  105.815081]  el0_svc_naked+0x30/0x34
[  105.818378] ---[ end trace 8d2322276b27879c ]---

Mark gcc_ufs_tx_symbol_0_clk as BRANCH_HALT_SKIP as well.

Fixes: 12d807cd34b8 ("clk: qcom: gcc-msm8996: Disable halt check on UFS clocks")
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06 10:48:42 -07:00
Bartosz Golaszewski
f917ff75ac clk: davinci: psc-da830: add a lookup entry for aemif clock
We want to use the ti-aemif platform driver for da830-evm. To make it
work we need a lookup entry for the aemif clock.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: David Lechner <david@lechnology.com>
2018-07-06 12:34:54 -05:00
Bartosz Golaszewski
b910f74a03 clk: davinci: psc-dm646x: use two lookup entries for the aemif clock
We want to be able to get the clock both from the board file by its
con_id and from the aemif driver by dev_id.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: David Lechner <david@lechnology.com>
2018-07-06 12:34:54 -05:00
Bartosz Golaszewski
8d1a83faa6 clk: davinci: psc-dm644x: use two lookup entries for the aemif clock
We want to be able to get the clock both from the board file by its
con_id and from the aemif driver by dev_id.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: David Lechner <david@lechnology.com>
2018-07-06 12:34:54 -05:00
Bartosz Golaszewski
63521abc15 clk: davinci: psc-dm365: use two lookup entries for the aemif clock
We want to be able to get the clock both from the board file by its
con_id and from the aemif driver by dev_id.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: David Lechner <david@lechnology.com>
2018-07-06 12:34:54 -05:00
Bartosz Golaszewski
a82c02e5b8 clk: davinci: psc-da850: remove the 'davinci_nand.0" lookup
Since commit a8e3923ab571 ("mtd: rawnand: davinci: don't acquire and
enable clock") we no longer acquire the aemif clock from the davinci
nand driver - we only do it from the ti-aemif driver. Remove the nand
entry from the psc lookup table.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: David Lechner <david@lechnology.com>
2018-07-06 12:33:57 -05:00
Elaine Zhang
243229b111 clk: rockchip: add clock controller for px30
Add the clock tree definition for the new px30 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-07-06 19:17:57 +02:00
Elaine Zhang
956060a527 clk: rockchip: add support for half divider
The new Rockchip socs have optional half divider:
The formula is shown as:
	freq_out = 2*freq_in / (2*div + 3)
Is this the same for all of new SoCs.

So we use "branch_half_divider" + "COMPOSITE_NOMUX_HALFDIV \
DIV_HALF \ COMPOSITE_HALFDIV \ CMPOSITE_NOGATE_HALFDIV"
to hook that special divider clock-type into our clock-tree.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-07-06 19:17:57 +02:00
Amit Nischal
cfb8282e18 clk: qcom: Enable clocks which needs to be always on for SDM845
There are certain clocks which needs to be always enabled for system
operation. Add support for the same by adding 'CLK_IS_CRITICAL' flag
for such clocks.

Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-03 10:10:36 -07:00
Philipp Puschmann
a7047564fe clk: imx6: fix video_27m parent for IMX6QDL_CLK_CKO1_SEL
q/dl datasheets list the 5th selection value for ck01_sel as
video_27M_clk_root.

By replacing the dummy value we then can set IMX6QDL_CLK_VIDEO_27M
as parent for IMX6QDL_CLK_CKO1_SEL.

Signed-off-by: Philipp Puschmann <pp@emlix.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-29 11:45:34 -07:00
Anson Huang
4a2eaa8e25 clk: imx6ul: remove clks_init_on array
Clock framework will enable those clocks registered
with CLK_IS_CRITICAL flag, so no need to have
clks_init_on array during clock initialization now.

ARM clock is busy divider type which has the
CLK_IS_CRITICAL flag set by default when registered.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-29 11:43:56 -07:00
Anson Huang
debef195bd clk: imx6ul: add GPIO clock gates
i.MX6UL has GPIO clock gates in CCM CCGR,
add them into clock tree for clock management.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-29 11:41:19 -07:00
Anson Huang
566f5b67fc clk: imx6sx: remove clks_init_on array
Clock framework will enable those clocks registered
with CLK_IS_CRITICAL flag, so no need to have
clks_init_on array during clock initialization now.

ARM clock is busy divider type which has the
CLK_IS_CRITICAL flag set by default when registered.

IPG clock has no clock gate and its parent AHB clock
is busy divider type, so no need to add CLK_IS_CRITICAL
flag for IPG clock.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-29 11:29:35 -07:00
Anson Huang
8e12ce9954 clk: imx6sl: remove clks_init_on array
Clock framework will enable those clocks registered
with CLK_IS_CRITICAL flag, so no need to have
clks_init_on array during clock initialization now.

ARM clock is busy divider type which has the
CLK_IS_CRITICAL flag set by default when registered.

IPG clock has no clock gate and its parent AHB clock
is busy divider type, so no need to add CLK_IS_CRITICAL
flag for IPG clock.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-29 11:28:31 -07:00
Anson Huang
54614d1218 clk: imx6q: remove clks_init_on array
Clock framework will enable those clocks registered
with CLK_IS_CRITICAL flag, so no need to have
clks_init_on array during clock initialization now.

ARM clock is busy divider type which has the
CLK_IS_CRITICAL flag set by default when registered.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-29 11:28:16 -07:00
Mike Looijmans
e8f127caf6 clk-si514, clk-si544: Implement prepare/unprepare/is_prepared operations
This adds prepare/unprepare/is_prepared functionality to the drivers for
the SI544 and SI514 chips, allowing the clock output to be disabled when
the clock is not in use.

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-29 10:59:40 -07:00