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Enable the x4 PCIe and M.2 Key E slots on Jetson TX1. The Key E slot is
currently untested due to lack of hardware.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
Add the PCIe host bridge found on Tegra X1. It implements two root ports
that support x4 and x1 configurations, respectively.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
This is a combination of the the Intel algorithm implemented using SSE
and PCLMULQDQ instructions from arch/x86/crypto/crc32-pclmul_asm.S, and
the new CRC32 extensions introduced for both 32-bit and 64-bit ARM in
version 8 of the architecture. Two versions of the above combo are
provided, one for CRC32 and one for CRC32C.
The PMULL/NEON algorithm is faster, but operates on blocks of at least
64 bytes, and on multiples of 16 bytes only. For the remaining input,
or for all input on systems that lack the PMULL 64x64->128 instructions,
the CRC32 instructions will be used.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This is a transliteration of the Intel algorithm implemented
using SSE and PCLMULQDQ instructions that resides in the file
arch/x86/crypto/crct10dif-pcl-asm_64.S, but simplified to only
operate on buffers that are 16 byte aligned (but of any size)
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
pci_mcfg_lookup() is the external interface to the generic MCFG code.
Previously it merely looked up the ECAM base address for a given domain and
bus range. We want a way to add MCFG quirks, some of which may require
special config accessors and adjustments to the ECAM address range.
Extend pci_mcfg_lookup() so it can return a pointer to a pci_ecam_ops
structure and a struct resource for the ECAM address space. For now, it
always returns &pci_generic_ecam_ops (the standard accessor) and the
resource described by the MCFG.
No functional changes intended.
[bhelgaas: changelog]
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
On x86 and ia64, we have treated all ACPI _CRS resources of PNP0A03 host
bridge devices as "producers", i.e., as host bridge windows. That's partly
because some x86 BIOSes improperly used "consumer" descriptors to describe
windows and partly because Linux didn't have good support for handling
consumer and producer descriptors differently.
One result is that x86 BIOSes describe host bridge "consumer" resources in
the _CRS of a PNP0C02 device, not the PNP0A03 device itself. On arm64 we
don't have a legacy of firmware that has this consumer/producer confusion,
so we can handle PNP0A03 "consumer" descriptors as host bridge registers
instead of windows.
Exclude non-window ("consumer") resources from the list of host bridge
windows. This allows the use of "consumer" PNP0A03 descriptors for bridge
register space.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Currently we use one shared global acpi_pci_root_ops structure to keep
controller-specific ops. We pass its pointer to acpi_pci_root_create() and
associate it with a host bridge instance for good. Such a design implies
serious drawback. Any potential manipulation on the single system-wide
acpi_pci_root_ops leads to kernel crash. The structure content is not
really changing even across multiple host bridges creation; thus it was not
an issue so far.
In preparation for adding ECAM quirks mechanism (where controller-specific
PCI ops may be different for each host bridge) allocate new
acpi_pci_root_ops and fill in with data for each bridge. Now it is safe to
have different controller-specific info. As a consequence free
acpi_pci_root_ops when host bridge is released.
No functional changes in this patch.
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
The static MCFG table tells us the base of ECAM space, but it does not
reserve the space -- the reservation should be done via a device in the
ACPI namespace whose _CRS includes the ECAM region.
Use acpi_resource_consumer() to check whether the ECAM space is reserved by
an ACPI namespace device. If it is, emit a message showing which device
reserves it. If not, emit a "[Firmware Bug]" warning.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Use a local "struct device *dev" for brevity. No functional change
intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
.inst being largely broken with older binutils, it'd be better not
to emit it altogether when detecting such configuration (as it
leads to all kind of horrors when using alternatives).
Generalize the __emit_inst macro and use it extensively in
asm/sysreg.h, and make it generate a .long when a broken gas is
detected. The disassembly will be crap, but at least we can write
semi-sane code.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Binutils version up to (and including) 2.25 have a pathological
behaviour when it comes to mixing .inst directive and arithmetic
involving labels. The assembler complains about non-constant
expressions and compilation stops pretty quickly.
In order to detect this and work around it, let's add a bit of
detection code that will set the CONFIG_BROKEN_GAS_INST option
should a broken gas be detected.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The asm/opcodes.h file is now gone, but probes.h still references it
for not obvious reason. Removing the #include directive fixes
the compilation.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Couple conflicts resolved here:
1) In the MACB driver, a bug fix to properly initialize the
RX tail pointer properly overlapped with some changes
to support variable sized rings.
2) In XGBE we had a "CONFIG_PM" --> "CONFIG_PM_SLEEP" fix
overlapping with a reorganization of the driver to support
ACPI, OF, as well as PCI variants of the chip.
3) In 'net' we had several probe error path bug fixes to the
stmmac driver, meanwhile a lot of this code was cleaned up
and reorganized in 'net-next'.
4) The cls_flower classifier obtained a helper function in
'net-next' called __fl_delete() and this overlapped with
Daniel Borkamann's bug fix to use RCU for object destruction
in 'net'. It also overlapped with Jiri's change to guard
the rhashtable_remove_fast() call with a check against
tc_skip_sw().
5) In mlx4, a revert bug fix in 'net' overlapped with some
unrelated changes in 'net-next'.
6) In geneve, a stale header pointer after pskb_expand_head()
bug fix in 'net' overlapped with a large reorganization of
the same code in 'net-next'. Since the 'net-next' code no
longer had the bug in question, there was nothing to do
other than to simply take the 'net-next' hunks.
Signed-off-by: David S. Miller <davem@davemloft.net>
ARM and arm64 Xen ports share a number of headers, leading to
packaging issues when these headers needs to be exported, as it
breaks the reasonable requirement that an architecture port
has self-contained headers.
Fix the issue by moving the 5 header files to include/xen/arm,
and keep local placeholders to include the relevant files.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Add neta nodes for network support both in device tree for the SoC and
the board.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The core and the cluster sleep state entry latencies can't be same as
cluster sleep involves more work compared to core level e.g. shared
cache maintenance.
Experiments have shown on an average about 100us more latency for the
cluster sleep state compared to the core level sleep. This patch fixes
the entry latency for the cluster sleep state.
Fixes: 28e10a8f3a03 ("arm64: dts: juno: Add idle-states to device tree")
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: "Jon Medhurst (Tixy)" <tixy@linaro.org>
Reviewed-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The opcodes.h drags in a lot of definition from the 32bit port, most
of which is not required at all. Clean things up a bit by moving
the bare minimum of what is required next to the actual users,
and drop the include file.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Under CONFIG_DEBUG_PREEMPT=y, this_cpu_ptr() ends up calling back into
raw_smp_processor_id(), resulting in some hilariously catastrophic
infinite recursion. In the normal case, we have:
#define this_cpu_ptr(ptr) raw_cpu_ptr(ptr)
and everything is dandy. However for CONFIG_DEBUG_PREEMPT, this_cpu_ptr()
is defined in terms of my_cpu_offset, wherein the fun begins:
#define my_cpu_offset per_cpu_offset(smp_processor_id())
...
#define smp_processor_id() debug_smp_processor_id()
...
notrace unsigned int debug_smp_processor_id(void)
{
return check_preemption_disabled("smp_processor_id", "");
...
notrace static unsigned int check_preemption_disabled(const char *what1,
const char *what2)
{
int this_cpu = raw_smp_processor_id();
and bang. Use raw_cpu_ptr() directly to avoid that.
Fixes: 57c82954e77f ("arm64: make cpu number a percpu variable")
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Install the callbacks via the state machine and let the core invoke
the callbacks on the already online CPUs.
Signed-off-by: Anna-Maria Gleixner <anna-maria@linutronix.de>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: rt@linutronix.de
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/20161126231350.10321-17-bigeasy@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
There is no requirement to keep the sysfs files around until the CPU is
completely dead. Remove them during the DOWN_PREPARE notification. This is
a preparatory patch for converting to the hotplug state machine.
Signed-off-by: Anna-Maria Gleixner <anna-maria@linutronix.de>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: rt@linutronix.de
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/20161126231350.10321-16-bigeasy@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This patch provides APEI arch-specific bits for ARM64
Meanwhile,
(1) Move HEST type (ACPI_HEST_TYPE_IA32_CORRECTED_CHECK) checking to
a generic place.
(2) Select HAVE_ACPI_APEI when EFI and ACPI is set on ARM64, because
arch_apei_get_mem_attribute is using efi_mem_attributes() on
ARM64.
Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
Tested-by: Jonathan (Zhixiong) Zhang <zjzhang@codeaurora.org>
Signed-off-by: Fu Wei <fu.wei@linaro.org>
[ Fu Wei: improve && upstream ]
Acked-by: Hanjun Guo <hanjun.guo@linaro.org>
Tested-by: Tyler Baicar <tbaicar@codeaurora.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This patch fixes the ARM64 CE CCM implementation decryption by
using skcipher_walk_aead_decrypt instead of skcipher_walk_aead,
which ensures the correct length is used when doing the walk.
Fixes: cf2c0fe74084 ("crypto: aes-ce-ccm - Use skcipher walk interface")
Reported-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
The PCIe root complex on Juno translates the MMIO mapped
at 0x5f800000 to the PIO address range starting at 0
(which is common because PIO addresses are generally < 64k).
Correct the DT to reflect this.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- new SoC support: S912/GXM series (8x A53)
- new boards: Nexbox A1 (S912), Nexbox A95X (S905X)
- resets for 2nd USB PHY
- update SCPI compatible for pre-v1.0 devices
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJYPI60AAoJEFk3GJrT+8ZlaaQQAJPdYxPKy00y6tM/adzqMsUY
/+HPHM6JgmMKkntHDMB0YRTtejYEhrgdWSHMlRnVhpPHeY/EU7a0+XAy6KIqnYzv
hWqHQFC4LVshh7/EwfN81iPYW8GXpZxXogREvYSWxJrxf7ISH4plEN4aq8JyWpmZ
ojAZOzc3nV9MvCdElfPqzo+tyCW8SDw5LDL8YdhF4huL/x3BC8wnqDV51yZvx1Re
CW3s8waEv94/DsoQhNc8ALZVwu2g94ygLWYUIZSNvPc3JpW73QO26qhf04FVLWO+
clBsjsejtJcPICTmeMeiBq7+awyigoPZOc+cP4LUhtRjPLUBlecPlb53jHukTrT7
0ahSAVH3NxBfXbeafkHHlXoy96SFdXsv6tl61XPBjrF/yn8z8BV0et0zI9mfrqq5
GjbZZegrfLodPYfI4VLbgGiBtYJQFU+i54e3jjYT1X1/bLVaYB4U9Dr4yMq53h5J
FL003w9jBO4BB/KsxGMyF3gGmBXrrR1UycOflzGwdiIkgpcx9zLxdUn4xDnkEmWD
peW+Qd3NeYRMW+8Xi8RzOOaXMkAubHr2lh2LPTUpGZ+RYmZ3qGACM5D7szIGgPWA
7vzuzcEeEzD8QVo5pnvlLIkSRmNV7b4YQMAv39fXrG34RGmN/oFLR/SFoYiPKLMI
jm+/R1hO7SUa0FNzoFry
=kgDs
-----END PGP SIGNATURE-----
Merge tag 'amlogic-dt64-2-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt64
Pull "Amlogic 64-bit DT updates for v4.10, round 2" from Kevin Hilman:
- new SoC support: S912/GXM series (8x A53)
- new boards: Nexbox A1 (S912), Nexbox A95X (S905X)
- resets for 2nd USB PHY
- update SCPI compatible for pre-v1.0 devices
* tag 'amlogic-dt64-2-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible
ARM64: dts: meson-gxl: Add support for Nexbox A95X
ARM64: dts: meson-gxm: Add support for the Nexbox A1
ARM64: dts: Add support for Meson GXM
ARM64: dts: meson-gxbb: add the USB reset also to the second USB PHY
Add clock controller device nodes, including one top clock controller,
two low speed clock controllers and one audio clock controller.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJYPDsqAAoJEFBXWFqHsHzOl5cH/iifyZ+RRLVuZBKRFM2TEq6T
0DFYvL+wQFQG74b3W8zT50r9ej5NLDvz7yMoqm2Njd/Qn2zM+WA8vxyhTES3JsqF
PIzbaYMaYfxMesGIfdCDFQ85g4TdKISCqEMiMrgNFynol6Yk3VHzjT7ODYPAzR/k
DZ7tRx1WW7dGLH4EsGZDo1dwC8zbWWoi0J8epbq3qgOXAZ5r5o8TZ4JCIMciqaXc
VaQVx/+3qK5rmW+b5BkPk8lFNHEPfi27m/NeHTebWg0YZ+VzvuoS3tAvJl5f1170
d21LvukXnrquLdj1KaD0LQOKP38oSGFp/1l9QsYfHHKnyIZPk17RNrW0wvRg5Zg=
=+8XT
-----END PGP SIGNATURE-----
Merge tag 'zte-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64
Pull "ZTE arm64 device tree update for 4.10" from Shawn Guo:
Add clock controller device nodes, including one top clock controller,
two low speed clock controllers and one audio clock controller.
* tag 'zte-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: zx: Add clock controller nodes
- fix some dtc compiler warnings
-----BEGIN PGP SIGNATURE-----
iQJIBAABCAAyFiEE2MW6uuYZ+0zBfpF41kg+k28NbwgFAlg4AYgUHGpzemhhbmdA
bWFydmVsbC5jb20ACgkQ1kg+k28Nbwgagw//V2xn6tlMIniGrEFjeePy3EQs3EpJ
AKzJ4/XvJItN5cheNbg4aoCLMa6LZuz7P0LhwcIxm1v9pIgx0qBhsElS6UuDpUs8
XszCryYtpkFmT3MHsRX5qU2zPjHsQn5MqIi0V4SQeEc/ELSZAaroqiC85bjo8Qoy
jYccHVPxwmdFZbIuNQNyg+GalpEyHo3jbOumc07dcf7z9zup3y2oknBJ+19v9Cs2
7zl9/i4SOlRQfXBTyYqmz5aAsAvffMSEYDmXdwLirZHr3W5ZCbg791NLG72MxeKl
iuLKvNbNUyumiUxVAKey4V1Yqa75w2JyDMNpy0yrmbgukD1zR48MLg3Zak9wvuJH
i9F3Iwd4+WiwihA+ulVwDYLICf/xofV+6CcxXSveHKnn8UFHK8qpdjTX0NAxTi94
61epxAmubpQ/mbLtrH0nJiJP6RvghvZHjz7gDRFvPapSefSU8hEM/RI39o9U20hR
vYDFLb0m9WYhJvuBXgXVM7gbDQPrErQwyL+/SEtIrjnnHt74V4iPhECm7m8fTgL7
1zFj4Vq2iwsNyy0vEPINzxc0hlmYVzwpKKaMof5HdyR5a7vqm6KsmozDBavyLOar
dYTrZeIUqmtwozBUHdpVQv/DKRs1IcjNuMM3uKEurQMfgIj2gRKCKOJghVgs9xSu
fgqkBWEkW6ad3yM=
=JqjI
-----END PGP SIGNATURE-----
Merge tag 'berlin64-dt-for-v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/jszhang/linux-berlin into next/dt64
Pull "Berlin64 DT changes for v4.10" from Jisheng Zhang:
- fix some dtc compiler warnings
* tag 'berlin64-dt-for-v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/jszhang/linux-berlin:
arm64: dts: berlin4ct-dmp: add missing unit name to /memory node
arm64: dts: berlin4ct-stb: add missing unit name to /memory node
arm64: dts: berlin4ct: add missing unit name to /soc node
as the binding doc for the 32bit rk1108 eval board to prevent it
from conflicting with the recently added 64bit px5 board.
-----BEGIN PGP SIGNATURE-----
iQEtBAABCAAXBQJYNj30EBxoZWlrb0BzbnRlY2guZGUACgkQ86Z5yZzRHYEoJQf/
WaANx7eR9cLkinPv6H123jeHAtMdvLFHmwb9kr2DwwNs6C9UxIsp9VddpG7XMSpI
bQLES0o0MALAAzIJH1oBb2wOWfDRWB/oXa/bSWXScbRXML+fH9ew1i1FaQQRDPHP
0/nm6GMbRZfMEraZHzTEY9duobLhbBH2va9GBv7M453D65B26c+ECvgbjULkI6My
qAdy5nN4Fb2YhxlZJz+WQQt59MNBT6nw8ObNPgKmSI18vB8BnQxqIEfo1gCuW+Iz
Sz+367EhVDtSW8cMWLttK6wB2iiiYGD0TOYfEeZS1zWavQlqDpFxFgZ66AKXdTxA
OYuAB8AKkTfa8NmejAUR2Q==
=PZ7U
-----END PGP SIGNATURE-----
Merge tag 'v4.10-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64
Pull "Rockchip dts64 changes for 4.10" from Heiko Stübner:
Some more powerdomains and usb2-otg support for the rk3399 as well
as the binding doc for the 32bit rk1108 eval board to prevent it
from conflicting with the recently added 64bit px5 board.
* tag 'v4.10-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
dt-bindings: add rockchip RK1108 Evaluation board
arm64: dts: rockchip: add usb2-phy otg-port support for rk3399
arm64: dts: rockchip: add pd_sd power-domain node for rk3399
arm64: dts: rockchip: add eMMC's power domain support for rk3399
arm64: dts: rockchip: add backlight support for rk3399 evb board
arm64: dts: rockchip: add gmac needed pclk for rk3399 pd
to basically boot.
-----BEGIN PGP SIGNATURE-----
iQEtBAABCAAXBQJYNvxvEBxoZWlrb0BzbnRlY2guZGUACgkQ86Z5yZzRHYH13Af9
GN3Rx9JrPOKxmp8yQrjf2IvtbRCNcyJsYAcT2C33KFrT+jZE087i+BdMZ9cniwr/
Y3w2JLyi6DS2aeoEZnYDsSQiBNudKKOeyDih5uI+oFDPQfmmfPfjuJUW5NrnpHSd
SLmXADAwjkB46o7Z1gFwquhXB+LcxjsYE5eu7Eda4pSHuBw2ZtNMMrZNDujJx/vU
zu36utDBWYFx6yMx32U1TYz3pf9cbi784j/Y5wr1zSCmuOgS2AZpl8KFC//92ZtU
Wi8T3sRBupun99/pVj+xvWtB9aHdWr8QxeVkRIUhx5XpM7njy9rX7QcJIDMm4kBf
uSbKZCh/uAjRjT/TpQiOsw==
=Fv2o
-----END PGP SIGNATURE-----
Merge tag 'v4.10-rockchip-defconfig64' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/arm64
Pull "Rockchip defconfig64 changes for 4.10" from Heiko Stübner:
64bit defconfig changes to allow arm64 Rockchip socs
to basically boot.
* tag 'v4.10-rockchip-defconfig64' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: defconfig: allow rk3399-based boards to boot from mmc and usb
arm64: defconfig: enable RK808 components
arm64: defconfig: enable I2C and DW MMC controller on rockchip platform
The sysfs ABI to GPIO is marked obsolete and should not be
encouraged. Users should be encouraged to switch to using the
character device.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Add SDHC xo clk and 1.8V DDR support
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYNos9AAoJEFKiBbHx2RXVWO8P/iSHtUP5UwiaX3+G86zkazvV
CIhufAArFxIRvMtRcbk1qIhrfA5c43aBoYx6ibcL6V2T2fWnJRBBJVvNZq4+htgR
U6lbiwF38E/e9zqmbseUtdfUo6Lh7KGvOHevxcu9sKa8rOiinmZ8jjRE2o5ypQhZ
jMEL7ScWFmwSL/nszD1UOiPBDuuBQyIqy+440oeRlIfRzJzonQVKTH+MJ92xqMx2
lfIzEutW33uK9Wz3rbwnz/FeaOubhj7S6kKBjJEvOrOOuSQcuuQty4bvn12ZNdyJ
cvb8HyrU8R9YOk6A1XrObpeP/z8WVydP6QlaGdxJ3t5Ma04JoQBaNeKcKV25AmS5
Row6++5E2Uijs5BTjdipqLGYjlHssH74i1BzyeWb5kiVIUMYG+aAZd1EUOkAaV6g
LqpUA9HWGKkHORpYq6EP3etYyZWQt7VXfIGtyiVWKNXAaKdQseMRSfOZve6kI/jY
VVb0mNQ29mYfWZV7Y1VP9UtrTtZ8gdrJArsNqsasu9Z6gQFsXUVbEVgliZjlFAUC
04VCuahZXMNKNNn3v1BDpN9j8UokTOOPij0UyWr6URwGc7tAdlMNEJOV6WL+PRZL
3JPcwP5As9lEQePhKH1Icc07OYg+WexpSPe8vhc5EOKTC7+GSrWnU2VIK71vtwSx
YrTqj/5ypJuOpGkkdySO
=EDYb
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-for-4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt64
Pull "Qualcomm ARM64 Updates for v4.10 - Part 2" from Andy Gross:
* Add SDHC xo clk and 1.8V DDR support
* tag 'qcom-arm64-for-4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
arm64: dts: qcom: msm8916: Add ddr support to sdhc1
ARM: dts: Add xo to sdhc clock node on qcom platforms
1. Add Performance Monitor Unit to Exynos7.
2. Add MFC, JPEG and Gscaler to Exynos5433 based TM2 board.
3. Cleanups and fixes for recently added TM2 and TM2E boards.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYNoEFAAoJEME3ZuaGi4PX90MP/2EWyj7J4a6vw3MpGkxtSbeO
tTWBdTgw8+9+MINW2HsGRn6WjzlFObF5Xl1LHyL2dBhVoJlLatWn0pjXqbo60u23
dQZ7jskBPlI3jH54rpKPUmd+Tk99dAYz7o6HCeqCLbBQT3bGHCxlueh5qZwRUcv3
EFFFsdpWtH97jI44olBKc/STzMWdRv5HOrpqtep+bNJINoEzEaWdIQNfpoEMrbs2
zcl5THbaHOl5cums67h1DHKxQOXQCtO4C6gon/MkELVvV4QzAhg4yj2mJLvEJieQ
AJnKDt+5X2XyIA1+EWAmilan3uUhxVPVkgFHRHZbuxSimL/5BQcMkvLDeMhG/ghr
ot5Rt0JmsY20hirCnApgk2yfor95TqmxhelMSqQ2T3IZjA4EvPovNR8xclBfKYAC
ctTT8yic15dkTcLxhiaq+DS993sKXKxbEBsu3jeIWRqKe8UrBe6+Eydsit/0rFt+
+6GkBRLMnJvVzoTsrcyYWflMh5eSKu4bma/MPtw8jQ/aMJX+XZ6yhLvXXM5OC7P1
GCmZlf5OZBIxbi9OjctB+iuQzgsBaiuVJbcYQu5HqYEtd7DLgqerjYmY4i0aGdWO
f2ZaKHfbFJjAVa8jduqo1HulTJTLagaXT1GABUtB/1YxTz6wpU8iB2i20ipMjm4w
dGbiLoGpCsl6QSSCo5hv
=/AE/
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt64-4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64
Pull "Samsung DeviceTree arm64 second update for v4.10" from Krzysztof Kozłowski:
1. Add Performance Monitor Unit to Exynos7.
2. Add MFC, JPEG and Gscaler to Exynos5433 based TM2 board.
3. Cleanups and fixes for recently added TM2 and TM2E boards.
* tag 'samsung-dt64-4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Enable HS400 mode for eMMC for TM2
arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash
arm64: dts: exynos: TM2 - add support for MFC video codec device
arm64: dts: exynos: TM2 - add support for JPEG codec device
arm64: dts: exynos: TM2 - add support for GScaler devices
arm64: dts: exynos: TM2 - remove unused UART3 and set clocks directly on CMU
arm64: dts: exynos: Assign parent clock of the clkout clock for TM2 board
arm64: dts: exynos: Move FSYS CMU configuration from Exynos5433 dtsi to TM2 dts
arm64: dts: exynos: Add missing parent clocks to audio block in Exynos5433 SoC
arm64: dts: exynos: Fix FSYS CMU parent clocks in Exynos5433 SoC
arm64: dts: exynos: Fix IRQ type flags for Exynos5433 SoC
arm64: dts: Add ARM PMU node for exynos7
please pull the following changes:
- Eric updates the ARMv8 defconfig to contain everything that is needed to run
a 64-bit kernel on the Raspberry Pi 3
- Scott enables the standard AT25 EEPROM driver as module for the ARM64 defconfig
- Martin enables the Raspberry Pi Thermal driver in the ARM64 defconfig
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJYM9aNAAoJEIfQlpxEBwcEZUIQAIIIIIzdvuqvrNR34ERLooCS
rmgUopq2+F53q2/A53zjdFXpUC655em7vz/pkDhnxdAqN8t2xb6ZIql8b/5BOsxv
OplYvSbwj34SVnBsRfF0zBJRhYg+gc4mebMbnMFciEigIZJXNyBbX/xMSHrbKzIm
gCCB7+agpB6ajzpOJ6pQemav4Nuxd5xLsE0Vx2Afh1DDNUyI/9CGeGxT5/46x6T/
Fz5C86zQW9iwvlZzDm3SztkV141eeGNpXSS966wqh16PD22fDEYFgBMTGaxp30v3
FdpV9Ig7YUEC5Dciev1Vepq50I+iqFAoIhHhIY28KDlpzp4mdvySEccwgZGDqAAi
7dSY+5mLGWoxgtYcIJO30c1u8j3BFMKwyWR94lnpdgJNgUME3qden+ndS2jnVP0y
esdNazOVKoR05qJS7hcB74+Kqu3cI0nP/jlEXloVy6APRyJi/g8q8A6z+fdAj5p5
k9jpIWnPIg82wqk1C5NEYkOzMvAn+YPPFlIDqlltDXs2xE+NTBljVSbogO6Y5tE+
XKvaUDhuBSj8R1mx9WaWQ4Iw+URk2KXVHxG8IXw7q55Qj4bS7vjQEpq4oNlRmYKK
/TBCiFSc/lUicJTEqm2uGXWFhBC0yekk8jlO6R5SGG1E6F+bHzC7N1H9Vr2vQysp
Ui1xKab2ZNtEL14XTfNc
=mWnY
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-4.10/defconfig-arm64' of http://github.com/Broadcom/stblinux into next/arm64
Pull "Broadcom defconfig-arm64 changes for 4.10" from Florian Fainelli:
This pull request contains Broadcom ARM64-based SoCs defconfig changes for 4.10,
please pull the following changes:
- Eric updates the ARMv8 defconfig to contain everything that is needed to run
a 64-bit kernel on the Raspberry Pi 3
- Scott enables the standard AT25 EEPROM driver as module for the ARM64 defconfig
- Martin enables the Raspberry Pi Thermal driver in the ARM64 defconfig
* tag 'arm-soc/for-4.10/defconfig-arm64' of http://github.com/Broadcom/stblinux:
ARM64: bcm2835: add thermal driver to default config
arm64: defconfig: enable EEPROM_AT25 config option
arm64: Add BCM2835 (Raspberry Pi 3) support to the defconfig
4.10, please pull the following:
- Robin updates the Northstart 2 DTS to use the generic IOMMU binding
- Scott renames the Broadcom Northstar 2 binding document to use a standard name
including the brcm vendor prefix
- Kamal adds the QSPI Device Tree node to the Northstar 2 SoC and updates the
Northstar 2 SVK reference board DTS file with it enabled.
- Rob adds the Device Tree node for the Broadcom PDC (mailbox) hardware to the
Northstar 2 SoC
- Jon enables the SDIO1 block and adds proper PCIe PHYs Device Tree nodes to the
Northstar 2 SoC
- Ray adds required properties NAND controller properties to make NAND work on
the Northstar 2 SVK board, this was submitted as a 4.9 fixes and is included
here to resolve DTS file merges
- Andrea removes an incorrect power LED from the Raspberry Pi 3 DTS
- Andreas fixes the compatible string for the BCM2837 (Raspberry Pi 3)
- Eric defines standard pinctrl groups in the BCM2835 GPIO node
- Gerd adds definitions for the pinctrl groups and updates the PWM, I2C and SDHCI nodes
to use their appropriate pinctrl functions
- Linus adds names for the Raspberry Pi GPIO lines based on the datasheet
- Martin adds the DT binding and nodes for the Raspberry Pi firmware thermal block
- Stefan fixes a few typos with respect to the BCM2835 mailbox binding example and
Device Tree nodes he also uses the proper DTSI file to define the USB host mode
for the USB Device Tree nodes
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJYM9SvAAoJEIfQlpxEBwcE80YQAOfjCKEXNSWJEAMpgsCo1oEf
6peBNi+y6AZCkNa+B1L9G2RY1B63OJKb+0HzAzj07cqbfu6r9UGhJEncnvuTnt6Q
iLZqoxDAKINNDT4tQBvPfdI8mF7ChNQ1RaJEKRh5/eaz9feKbp0QP216oNyzdOTX
4fUCBfgAxl6q1aNv4f4tcTdy30NllQddulLumYq5W7ElAP3CYeUGszoJ6npDqX6Z
p2p42OMczOoU0xDH/a5BJBQW/ZbylCgFOSnGtQp6RnzOB6iBxKYDOCkMRfVLIPSg
uC+7XSEpYAxNPRAHE5JxtADEdDKZ4zdKne8SpadixBPY8vAWguEhiOAFRqTKYpXr
UY8itk9NMx8BnI6Fl4hU6tFs3Yx9+6PdHX0nWeR1OE2gzYpnVKOdeeS3+nWHctWm
Z2wyglSvEpzMpaCzr2/rgDXW30BUTGtRCD7rYJ7MhwItkXm4yIN8pkLw83Zxss4d
3J30QQoQ5s9Fye0Or4Z/PQiw3AtUJnH1u59BAE2GmrHVgs4pUaxuU4lt+LYBZtoM
hA+pzFDeNmK/fOumjFhmvZwrCG1AON2cJRExMG6l3x9sxV2FDw1Awr4sina7ZFcO
pbkvHmTXcGHNh7kqHeEU51r4tkkA97ZHeKGrntRSfsMNyu74xzOSsjEEf5MKMm5s
2xX2RhehADTDa5xPDJwG
=a4fP
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-4.10/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64
Pull "Broadcom devicetree-arm64 changes for 4.10" from Florian Fainelli:
This pull request contains Broadcom ARM64 based SoC Device Tree changes for
4.10, please pull the following:
- Robin updates the Northstart 2 DTS to use the generic IOMMU binding
- Scott renames the Broadcom Northstar 2 binding document to use a standard name
including the brcm vendor prefix
- Kamal adds the QSPI Device Tree node to the Northstar 2 SoC and updates the
Northstar 2 SVK reference board DTS file with it enabled.
- Rob adds the Device Tree node for the Broadcom PDC (mailbox) hardware to the
Northstar 2 SoC
- Jon enables the SDIO1 block and adds proper PCIe PHYs Device Tree nodes to the
Northstar 2 SoC
- Ray adds required properties NAND controller properties to make NAND work on
the Northstar 2 SVK board, this was submitted as a 4.9 fixes and is included
here to resolve DTS file merges
- Andrea removes an incorrect power LED from the Raspberry Pi 3 DTS
- Andreas fixes the compatible string for the BCM2837 (Raspberry Pi 3)
- Eric defines standard pinctrl groups in the BCM2835 GPIO node
- Gerd adds definitions for the pinctrl groups and updates the PWM, I2C and SDHCI nodes
to use their appropriate pinctrl functions
- Linus adds names for the Raspberry Pi GPIO lines based on the datasheet
- Martin adds the DT binding and nodes for the Raspberry Pi firmware thermal block
- Stefan fixes a few typos with respect to the BCM2835 mailbox binding example and
Device Tree nodes he also uses the proper DTSI file to define the USB host mode
for the USB Device Tree nodes
* tag 'arm-soc/for-4.10/devicetree-arm64' of http://github.com/Broadcom/stblinux: (23 commits)
arm64: dts: NS2: Add PCI PHYs
arm64: dts: NS2: enable sdio1
ARM64: dts: bcm2837-rpi-3-b: remove incorrect pwr LED
ARM64: bcm2835: dts: add thermal node to device-tree of bcm2837
ARM: bcm2835: Add names for the Raspberry Pi GPIO lines
ARM: bcm2835: dts: add thermal node to device-tree of bcm283x
dt: bindings: add thermal device driver for bcm2835
arm64: dts: Add Broadcom Northstar2 device tree entries for PDC driver.
ARM: dts: bcm283x: fix typo in mailbox address
DT: binding: bcm2835-mbox: fix address typo in example
ARM64: dts: bcm2835: Fix bcm2837 compatible string
arm64: dts: Update Broadcom NS2 to generic IOMMU binding
arm64: dts: Updated NAND DT properties for NS2 SVK
arm64: dts: rename ns2.txt to brcm,ns2.txt
ARM64: dts: Add QSPI Device Tree node for NS2
ARM64: dts: bcm283x: Use dtsi for USB host mode
ARM: dts: bcm283x: drop alt3 from &gpio
ARM: dts: bcm283x: add pinctrl group to &sdhci, drop pins from &gpio
ARM: dts: bcm283x: add pinctrl group to &i2c1, drop pins from &gpio
ARM: dts: bcm283x: add pinctrl group to &i2c0, drop pins from &gpio
...
This adds initial support for Tegra186, the P3310 processor module as
well as the P2771 development board. Not much is functional, but there
is enough to boot to an initial ramdisk with debug serial output.
-----BEGIN PGP SIGNATURE-----
iQIwBAABCAAaBQJYMsltExx0cmVkaW5nQG52aWRpYS5jb20ACgkQ3SOs138+s6HY
8g/7Bf5ieQkhnW4fHAicTnX+5zXJEiQZrlCYfOzNq1nyGi/NBrcAVajQTRhL1g/k
cSKESq7OrjmhAlhHUWEaHHicnzax6jLwrUaj/ozcAti5m8iXOz+JnD184fE3CqcJ
5DGp26k0vrPcc47u2SIWjx1u4coUssYxLjsyoR2NJPZkWYMKpPL7rK969PizlAID
ajbixuLgd4N6utWPz2o3j+23hXf03rXaPrZ6d9khsAvGQBkQx4QJAIbsKJrBbGR9
UbZbTDPgJGmvpa12IK0tblTKbHahhAkxRj5dX8F4eCwZBVmYp9fx+qLLKKdzoO5R
pZmMQiT24j0RNlC4CTPRI7wVBr6x5m1UtcuEq9exipsdocC1/AAm9iD5U09gX41T
7kBcQ/mIl62CSxoaNNjSoHi+hK+HRyqIcR2tjWe+HhkJONCcPi7zUZvtSkM85n7v
8z26KxFJpjpXd+Bg8oC3eIBbYxZOBoa5YzK4zDCA5znrGD0HSxUHtetYFru5LX7u
sVLc+wXfAuqKS/uh8FzVtk/tTrjib82OngQkD5ofGn3IkXEuIueLU4o4C8VhNt1n
7bH3MwWoahcUWQiH1/GwXglw1X6J2wE6isvF9u08pYg0nIfZsSPvbRjRriZzgk1v
dyBsZxnLpWGJPxly5H+3u9+XUetKPuZZs2EQxzwauoUNIjo=
=iXdy
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-4.10-arm64-dt-numeric-ids' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64
Pull "arm64: tegra: Device tree changes for v4.10-rc1" from Thierry Reding:
This adds initial support for Tegra186, the P3310 processor module as
well as the P2771 development board. Not much is functional, but there
is enough to boot to an initial ramdisk with debug serial output.
* tag 'tegra-for-4.10-arm64-dt-numeric-ids' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Add NVIDIA P2771 board support
arm64: tegra: Enable PSCI on P3310
arm64: tegra: Add NVIDIA P3310 processor module support
arm64: tegra: Add GPIO controllers on Tegra186
arm64: tegra: Add SDHCI controllers on Tegra186
arm64: tegra: Add I2C controllers on Tegra186
arm64: tegra: Add serial ports on Tegra186
arm64: tegra: Add CPU nodes for Tegra186
arm64: tegra: Add Tegra186 support
The default value of 17 for CONFIG_LOG_BUF_SHIFT is much more suitable
than 14. The latter easily leads to lost kernel messages on systems with
only one CPU core.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
* Identify SoC and register with the SoC bus
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYNeyaAAoJENfPZGlqN0++1WsQAJ6Yq6mB9+TlmKQSDmspMd1X
cuswMJowQZSFWjiXT/3v6lUNBG7wJmXbJOWIu/V9HIAx3HXS860DRtEC0+CosZ1g
yP/+i8g5qHtYNtOG06RaP62gJql+nMizfvtTVNlFBz5/r6Pt6Cw2VKZm/J5eIenv
zjWwkCOH2JAcAfVu1JfqXNoNwkrPp/tbTXmodQsqm7WYNiwfk2gXNqKhROirWR0s
n2oHVhEts1Q82i116p1mx3m7CYvned5jqph06KyHWutbxNbGGi9ikIOmS0B6ayyw
TSU1lAsF2xIff1JDJpGkZoIZAt0NKAfSYzumz1s98Yj+8cXMVZ/IL/C4orkqV8fk
20K3ZYyBD3fDl38OtqGDOCTX7uOLumPCmoCLdKwmEYX2ig4PbK5pNbwQNMTFH4iE
iqGXaicbs94izsDg0hUMALfAI4oG7TwTEDGnmLfXbOx58FJPtw+VcxArt0QiaLaf
TdrNfVyl+wMu1cvOxqI3ftmzhlzpdoLoFNrZxPORAurEGN45SzDZylnLvfxByQy4
WixQPdS/pHofdKmvIVXIdVzxnO0xRmxAp1tZ8nYw4rkseSGvLnK9Z4d43kzvoTsr
IW+rJBBgLIcyor6HWrSgjWK9T15FEDBbrk5U1d06IViBdYwi1c6U8y80LCaAB+8j
y3IwB4GFFkiTUU6j3H75
=DnnT
-----END PGP SIGNATURE-----
Merge tag 'renesas-soc-match-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers
Merge "Renesas ARM Based SoC Match Updates for v4.10" from Simon Horman:
* Identify SoC and register with the SoC bus
* tag 'renesas-soc-match-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
soc: renesas: Identify SoC and register with the SoC bus
ARM: shmobile: Document DT bindings for Product Register
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Two branches were incorrectly sent without having the necessary
header file changes. Rather than back those out now, I'm replacing
the symbolic names for the clks and resets with the numeric
values to get 'make allmodconfig dtbs' back to work.
After the header file changes are merged, we can revert this
patch.
Fixes: 6bc37fa ("arm64: dts: add Allwinner A64 SoC .dtsi")
Fixes: 50784e6 ("dts: arm64: db820c: add pmic pins specific dts file")
Acked-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fix a missing statement that got lost in the skcipher conversion of
the CTR transform.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
When building the arm64 kernel with both CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
and CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y configured, the build breaks with
the following error:
arch/arm64/crypto/aes-neon-blk.o:(.bss+0x0): multiple definition of `aes_simd_algs'
arch/arm64/crypto/aes-ce-blk.o:(.bss+0x0): first defined here
Fix this by making aes_simd_algs 'static'.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* will/for-next/perf:
selftests: arm64: add test for unaligned/inexact watchpoint handling
arm64: Allow hw watchpoint of length 3,5,6 and 7
arm64: hw_breakpoint: Handle inexact watchpoint addresses
arm64: Allow hw watchpoint at varied offset from base address
hw_breakpoint: Allow watchpoint of length 3,5,6 and 7
Bit positions of CNTHCTL_EL2 are changing depending on HCR_EL2.E2H bit.
EL1PCEN and EL1PCTEN are 1st and 0th bits when E2H is not set, but they
are 11th and 10th bits respectively when E2H is set. Current code is
unintentionally setting wrong bits to CNTHCTL_EL2 with E2H set.
In fact, we don't need to set those two bits, which allow EL1 and EL0 to
access physical timer and counter respectively, if E2H and TGE are set
for the host kernel. They will be configured later as necessary. First,
we don't need to configure those bits for EL1, since the host kernel
runs in EL2. It is a hypervisor's responsibility to configure them
before entering a VM, which runs in EL0 and EL1. Second, EL0 accesses
are configured in the later stage of boot process.
Signed-off-by: Jintack Lim <jintack@cs.columbia.edu>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
readq and writeq type of assessors are not supported in AArch32, so we
need to specialise them and glue later with series of 32-bit accesses
on AArch32 side.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
It'd be better to switch to CMA... but before that done redirect
flush_dcache operation, so 32-bit implementation could be wired
latter.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
The workaround for Cavium ThunderX erratum 23154 has a homebrew
pipeflush built out of NOP sequences around the read of the IAR.
This patch converts the code to use the new nops macro, which makes it
a little easier to read.
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
The GIC system registers are accessed using open-coded wrappers around
the mrs_s/msr_s asm macros.
This patch moves the code over to the {read,wrote}_sysreg_s accessors
instead, reducing the amount of explicit asm blocks in the arch headers.
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Add the dts node for device configuration unit that provides
general purpose configuration and status for the device.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Acked-by: Scott Wood <oss@buserror.net>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
The skcipher conversion for ARM missed the select on CRYPTO_SIMD,
causing build failures if SIMD was not otherwise enabled.
Fixes: da40e7a4ba4d ("crypto: aes-ce - Convert to skcipher")
Fixes: 211f41af534a ("crypto: aesbs - Convert to skcipher")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Add the files that are generated by the recently merged OpenSSL
SHA-256/512 implementation to .gitignore so Git disregards them
when showing untracked files.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
