20048 Commits

Author SHA1 Message Date
Andrew Jeffery
ad5d102784 ARM: dts: ast2600-evb: Add pinmux properties for enabled MACs
All 2600-evb MACs use RGMII/MDIO.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01 15:33:20 +10:30
Andrew Jeffery
d29f8a6e42 ARM: dts: aspeed-g6: Add pinctrl properties to MDIO nodes
This way enabling the MDIO controllers automatically requests the right
pinmux configuration.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01 15:33:20 +10:30
Andrew Jeffery
9f5a341eb9 ARM: dts: aspeed-g6: Fix EMMC function in pinctrl dtsi
The binding was updated to better reflect the intended use of the
hardware and the existing function/groups for SD3 were dropped.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01 15:33:20 +10:30
Joel Stanley
a45d88725d ARM: dts: aspeed: ast2600evb: Use custom flash layout
The AST2600 u-boot and kernel images have outgrown the OpenBMC layout.
While BMC machines use 128MB SPI NOR chips, we only have 64MB on the EVB
so use a layout that has a smaller region for the ro and rw filesystems.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01 15:33:20 +10:30
Cédric Le Goater
6700acf666 ARM: dts: ast2600-evb: Enable FMC and SPI devices
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01 15:33:20 +10:30
Joel Stanley
8db6997f2b ARM: dts: aspeed: tacoma: Enable FMC and SPI devices
Tacoma has two SPI flash devices attached to the FMC, and one on the SPI
controller.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01 15:33:20 +10:30
Cédric Le Goater
f97fa21f48 ARM: dts: aspeed: rainier: Enable FMC and SPI devices
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01 15:33:20 +10:30
Brad Bishop
2efc118ce3 ARM: dts: aspeed: rainier: Add i2c devices
Add fan controllers, regulators, temperature sensors, power supplies
and regulators.

Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01 15:33:20 +10:30
Brad Bishop
99e3cfa266 ARM: dts: aspeed: rainier: Add mac devices
Rainier contains two NCSI network devices.

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01 15:33:20 +10:30
Brad Bishop
961216c135 ARM: dts: aspeed: Add Rainier system
Rainier is a new IBM server with POWER host processors and an AST2600
BMC.

Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01 15:33:20 +10:30
Brad Bishop
4caa4e302c ARM: dts: Add 128MiB OpenBMC flash layout
This is an alternate layout used by OpenBMC systems that require more
space on the BMC's flash. In addition to more space for the rootfs, it
supports a larger u-boot and Linux kernel FIT image.

The division of space is as follows:

 u-boot + env: 1MB
 kernel/FIT: 9MB
 rwfs: 86MB
 rofs: 32MB

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01 15:33:20 +10:30
Chicago Duan
d52ce2beca ARM: dts: aspeed: fp5280g2: Add LED configuration
Change BMC init-ok from GPIO to LED, which needs to blink when BMC
initialization is complete.

Use TAB to align some lines.

Signed-off-by: Chicago Duan <duanzhijia01@inspur.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01 15:33:20 +10:30
Eddie James
606bcdde67 ARM: dts: aspeed: tacoma: Enable I2C busses
Enable all the I2C busses on Tacoma and add the I2C slave devices that
exist on the busses.

Signed-off-by: Eddie James <eajames@linux.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01 15:33:20 +10:30
Joel Stanley
b58135ad1e ARM: dts: aspeed: Add Tacoma machine
This is an AST2600 based BMC card for a Power9 system.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01 15:33:19 +10:30
Cédric Le Goater
51d5d1bf73 ARM: dts: aspeed-g6: Add FMC and SPI devices
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01 15:33:19 +10:30
Brad Bishop
12ce8bd361 ARM: dts: aspeed-g6: Add lpc devices
Everything is the same as G5, except the devices have their own
interrupt now.

Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01 15:33:19 +10:30
Joel Stanley
2aed40eeb4 ARM: dts: aspeed-g6: Add VUART descriptions
The AST2600 has two VUART devices.

Reviewed-by: Eddie James <eajames@linux.ibm.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01 15:33:19 +10:30
Joel Stanley
9ee6d17b18 ARM: dts: aspeed-g6: Add i2c buses
The AST2600 has 16 I2C buses each with their own global IRQ line.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01 15:29:48 +10:30
Rashmica Gupta
8dbcb5b709 ARM: dts: aspeed-g6: Add gpio devices
The AST2600 has 208 normal GPIO pins and 36 1.8V GPIOs.

Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01 15:29:48 +10:30
Andrew Jeffery
311b57f051 ARM: dts: ast2600-evb: eMMC configuration
Enable the eMMC controller and limit it to 52MHz to avoid the host
controller reporting bus error conditions.

Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2019-11-01 15:29:48 +10:30
Tero Kristo
f586919066 ARM: dts: omap3: fix DPLL4 M4 divider max value
The maximum divider value for DPLL4 M4 divider appears wrong. For most
OMAP3 family SoCs this is 16, but it is defined as 32, which is maybe
only valid for omap36xx. To avoid any overflows in trying to write this
register, set the max to 16 for all omap3 family, except omap36xx. For
omap36xx the maximum is set to 31, as it appears value 32 is not working
properly.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Adam Ford <aford173@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
2019-10-31 15:33:26 +02:00
Mylène Josserand
0c25bfa7fa
ARM: dts: sun8i: a83t: a711: Add touchscreen node
Enable a FocalTech EDT-FT5x06 Polytouch touchscreen.

Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Signed-off-by: Maxime Ripard <mripard@kernel.org>
2019-10-31 13:34:57 +01:00
Cheng-Yi Chiang
bbf8f6fef7 ARM: dts: rockchip: Add HDMI audio support to rk3288-veyron-mickey
Add HDMI audio support to veyron-mickey. The sound card should expose
one audio device for HDMI.

Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Link: https://lore.kernel.org/r/20191028071930.145899-7-cychiang@chromium.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-31 11:49:56 +01:00
Cheng-Yi Chiang
d6707fb710 ARM: dts: rockchip: Add HDMI support to rk3288-veyron-analog-audio
All boards using rk3288-veyron-analog-audio.dtsi have HDMI audio.
Specify the support of HDMI audio on machine driver using
rockchip,hdmi-codec property so machine driver creates HDMI audio device.

Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Link: https://lore.kernel.org/r/20191028071930.145899-6-cychiang@chromium.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-10-31 11:48:27 +01:00
Tony Lindgren
8df81af177 Merge branch 'rng' into omap-for-v5.5/dt 2019-10-30 08:25:14 -07:00
Tony Lindgren
308607e554 ARM: dts: Configure omap3 rng
Looks like omap3 RNG is similar to the omap2 rng, let's get it working
by configring the dts node for it.

We must also add rng_ick to core_l4_clkdm as noted by Adam Ford.

And please note that the RNG is likely disabled on HS devices. At least
n900 does not have it accessible, and instead omap3-rom-rng driver must
be used. So let's tag RNG as disabled on n900 as noted by Pali Rohár
<pali.rohar@gmail.com>.

On am3517 at least the clocks need to be configured to get it working
as noted by Adam Ford, so let's tag it disabled for now.

Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: Adam Ford <aford173@gmail.com>
Cc: Pali Rohár <pali.rohar@gmail.com>
Cc: Sebastian Reichel <sre@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Tested-by: Adam Ford <aford173@gmail.com> #logicpd-torpedo-37xx-devkit
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-10-30 08:14:03 -07:00
Dmitry Osipenko
4053aa65c5 ARM: tegra: cardhu-a04: Add CPU Operating Performance Points
Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on
Cardhu A04.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29 20:29:17 +01:00
Dmitry Osipenko
c01afebd74 ARM: tegra: cardhu-a04: Set up voltage regulators for DVFS
Set minimum and maximum voltages, and couple CPU/CORE regulators.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29 20:29:17 +01:00
Dmitry Osipenko
c19c631a3c ARM: tegra: trimslice: Add CPU Operating Performance Points
Utilize common Tegra20 CPU OPP table. CPU voltage scaling is available
now on TrimSlice.

Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29 20:29:17 +01:00
Dmitry Osipenko
5ac1505008 ARM: tegra: paz00: Add CPU Operating Performance Points
Utilize common Tegra20 CPU OPP table. CPU DVFS is available now on
AC100.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29 20:29:17 +01:00
Dmitry Osipenko
a60e68f98f ARM: tegra: paz00: Set up voltage regulators for DVFS
Set minimum and maximum voltages, and couple CPU/CORE/RTC regulators.

Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29 20:29:17 +01:00
Dmitry Osipenko
875cf30a53 ARM: tegra: Add CPU Operating Performance Points for Tegra30
Operating Point are specified per HW version. The OPP voltages are kept
in a separate DTSI file because some boards may not define CPU regulator
in their device-tree if voltage scaling isn't necessary for them.

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29 20:29:16 +01:00
Dmitry Osipenko
584eca7060 ARM: tegra: Add CPU Operating Performance Points for Tegra20
Operating Point are specified per HW version. The OPP voltages are kept
in a separate DTSI file because some boards may not define CPU regulator
in their device-tree if voltage scaling isn't necessary, like for example
in a case of tegra20-trimslice which is outlet-powered device.

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29 20:29:16 +01:00
Dmitry Osipenko
663bd48727 ARM: tegra: Add Tegra30 CPU clock
All "geared" CPU cores share the same CPU clock.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29 20:29:16 +01:00
Dmitry Osipenko
dc6fdedf77 ARM: tegra: Add Tegra20 CPU clock
All CPU cores share the same CPU clock.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29 20:29:16 +01:00
Dmitry Osipenko
3193a063a2 ARM: tegra: Add External Memory Controller node on Tegra30
Add External Memory Controller node to the device-tree.

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29 20:29:16 +01:00
Dmitry Osipenko
e14dc5ea7c ARM: tegra: nyan-big: Add timings for RAM codes 4 and 6
Add timings for RAM codes 4 and 6 and a timing for 528mHz of RAM code 1,
which was missed due to the clock driver bug that is fixed now in all of
stable kernels.

Tested-by: Steev Klimaszewski <steev@kali.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29 20:29:15 +01:00
Dmitry Osipenko
cdc233fb03 ARM: tegra: Connect SMMU with Video Decoder Engine on Tegra30
Enable IOMMU support for the video decoder.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29 20:29:15 +01:00
Thierry Reding
a4563f5bf1 ARM: tegra: Add eDP power supplies on Venice2
The power supplies needed to drive eDP on Venice2 were never hooked up,
so things only worked because those regulators are already enabled by
other devices.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29 20:29:15 +01:00
Thierry Reding
5d089d42bc ARM: tegra: Add SOR0_OUT clock on Tegra124
This clock is needed for eDP to properly function, so add it to the SOR
device tree node.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29 20:29:14 +01:00
Philippe Schenker
05a6a629f0 ARM: tegra: Add stmpe-adc DT node to Toradex T30 modules
Add the stmpe-adc DT node as found on Toradex T30 modules

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-29 20:29:14 +01:00
Ondrej Jirman
e614f34125
ARM: dts: sun8i-a83t-tbs-a711: Fix WiFi resume from suspend
Without enabling keep-power-in-suspend, we can't wake the device
up using WOL packet, and the log is flooded with these messages
on resume:

sunxi-mmc 1c10000.mmc: send stop command failed
sunxi-mmc 1c10000.mmc: data error, sending stop command
sunxi-mmc 1c10000.mmc: send stop command failed
sunxi-mmc 1c10000.mmc: data error, sending stop command

So to make the WiFi really a wakeup-source, we need to keep it powered
during suspend.

Fixes: 0e23372080def7 ("arm: dts: sun8i: Add the TBS A711 tablet devicetree")
Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Maxime Ripard <mripard@kernel.org>
2019-10-29 08:44:13 +01:00
Olof Johansson
ab7822067f STM32 DT updates for v5.5, round 1
Highlights:
 ----------
 
 MPU part:
  -Add and enable ADC support on stm32mp157a-dk1
  -Add DAC support on stm32mp157c-ed1
  -Add and enable VREFBUF support on stm32mp157a-dk1
  -Add focaltech touchscreen on stm32mp157c-dk2
  -Add hdmi support on stm32mp157a-dk1
  -Fix issues seen during YAML DT validation
  -Fix regulators issues for all MPU boards
 
 MCU part:
  -Fix issues seen during YAML DT validation
 -----BEGIN PGP SIGNATURE-----
 
 iQJMBAABCgA2FiEEctl9+nxzUSUqdELdf5rJavIecIUFAl2y7XIYHGFsZXhhbmRy
 ZS50b3JndWVAc3QuY29tAAoJEH+ayWryHnCFy20P/jsx+9tDLGZAHCiPlnIu80gd
 XKjecdpVPTYYCef4cUxF6rkkJWbtdauvmys9xJH9EZetd0kwPF6otfo6hiQGsIB1
 +3ChAEzI6qHV5iEWl91AWCIyTuVo6dimJqXJCNLuldDMQbOlEbP4jHjD00ggn0r3
 tFhvhp/gXT21xt+t0kgHf3GJV8nQwwQw3NHCoqagnzHRZrURgwZM/ecYJs7uv3eu
 TGMmuNytxFl46JugVnWFYj2NgMrg/G0oqDR7SwieoEBqADEmkPDS2UkKPmuAe9BO
 3sknTu1Mf1yXlbWLeFOa9MLgiNRH7c5oLSWPkRnFe/GMlco0iJ+63r1ff4N5i5u0
 M5l0dJ0mL81RK6n1rubyaOdMBV25UIZ2QlL13tTPmVFbUj95pR9d4B6sxaqdJh3a
 8s6WYLnlyJZ8+WldcPURYCot4ezRy9o0vE5YN/FCW3NDdY0fEYXQVCbs/ufgmKNk
 K7jRleAr0SXk5IFRYgVxvkhbYWB80jKVPEGEhpBPAzrhvSmJqgHN2RdUXB+IRGyP
 IIFZT8UgodMxzrxA9bJStphet4nvItGW68G76FDXt2zS1rw4mLum6rKq+s3x3Fyp
 DiUP7ZfaaKLQbo/nG+AAIK4I3lWgI+lxG7uF5tG/6qFOyTqKmMiMXUFK7jisMZeQ
 yyyhkjAZXjBtmcKpXbgV
 =X4PA
 -----END PGP SIGNATURE-----

Merge tag 'stm32-dt-for-v5.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt

STM32 DT updates for v5.5, round 1

Highlights:
----------

MPU part:
 -Add and enable ADC support on stm32mp157a-dk1
 -Add DAC support on stm32mp157c-ed1
 -Add and enable VREFBUF support on stm32mp157a-dk1
 -Add focaltech touchscreen on stm32mp157c-dk2
 -Add hdmi support on stm32mp157a-dk1
 -Fix issues seen during YAML DT validation
 -Fix regulators issues for all MPU boards

MCU part:
 -Fix issues seen during YAML DT validation

* tag 'stm32-dt-for-v5.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
  ARM: dts: stm32: remove useless dma-ranges property for stm32f469
  ARM: dts: stm32: remove useless dma-ranges property for stm32f429
  ARM: dts: stm32: disable active-discharge for vbus_otg on stm32mp157a-avenger96
  ARM: dts: stm32: Fix active discharge usage on stm32mp157
  ARM: dts: stm32: change default minimal buck1 value on stm32mp157
  ARM: dts: stm32: add PWR regulators support on stm32mp157
  ARM: dts: stm32: remove useless interrupt from dsi node for stm32f469
  ARM: dts: stm32: add hdmi audio support to stm32mp157a-dk1 board
  ARM: dts: stm32: Add DAC support to stm32mp157c-ed1
  ARM: dts: stm32: Add DAC pins used on stm32mp157c-ed1
  ARM: dts: stm32: fix regulator-sd_switch node on stm32mp157c-ed1 board
  ARM: dts: stm32: remove usb phy-names entries on stm32mp157c-ev1
  ARM: dts: stm32: fix joystick node on stm32f746 and stm32mp157c eval boards
  ARM: dts: stm32: fix memory nodes to match with DT validation tool
  ARM: dts: stm32: add focaltech touchscreen on stm32mp157c-dk2 board
  ARM: dts: stm32: enable ADC support on stm32mp157a-dk1
  ARM: dts: stm32: add ADC pins used on stm32mp157a-dk1
  ARM: dts: stm32: Enable VREFBUF on stm32mp157a-dk1
  ARM: dts: stm32: move ltdc pinctrl on stm32mp157a dk1 board

Link: https://lore.kernel.org/r/02c39510-f36d-abbb-c76f-49aff07c0a08@st.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-10-28 08:53:17 -07:00
Fabio Estevam
f324c95290 ARM: dts: imx53-qsb: Use DRM bindings for the Seiko 43WVF1G panel
Currently the parallel panel that is supported is the CLAA WVGA panel,
which is the one that comes with the i.MX51 Babbage board.

The default parallel panel that goes with the imx53-qsb board is
the Seiko 43WVF1G LCD, so switch to the Seiko one.

While at it convert to DRM bindings.

The parallel display still remains disabled as the default display
port is the TVE output.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28 19:54:17 +08:00
Geert Uytterhoeven
ff84e9deae ARM: dts: imx53: Spelling s/configration/configuration/
Fix misspelling of "configuration".

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28 19:52:16 +08:00
Anson Huang
2c661547f2 ARM: dts: imx6ul-14x14-evk: Assign power supplies for magnetometer
On i.MX6UL 14x14 EVK board, mag3110's power is controlled by
sensor regulator, assign power supplies for mag3110 driver
to do power management.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28 16:56:08 +08:00
Anson Huang
516ab2eecb ARM: dts: imx6ul-14x14-evk: Fix the magnetometer node name
Node name is supposed to be generic, use "magnetometer" instead
of "mag3110" for magnetometer node.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28 16:56:06 +08:00
Anson Huang
09e2b10489 ARM: dts: imx6ul-14x14-evk: Add sensors' GPIO regulator
On i.MX6UL 14x14 EVK board, sensors' power are controlled
by GPIO5_IO02, add GPIO regulator for sensors to manage
their power.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28 16:55:51 +08:00
Anson Huang
c4e88bb794 ARM: dts: imx6ul: Disable gpt2 by default
i.MX GPT driver ONLY supports 1 instance, i.MX6UL already has
GPT1 enabled by default, so GPT2 should be disabled.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28 16:49:43 +08:00
Anson Huang
28e95b7dcc ARM: dts: imx7d: Add missing cooling device properties for CPUs
The cooling device properties "#cooling-cells" should either be present
for all the CPUs of a cluster or none. If these are present only for a
subset of CPUs of a cluster then things will start falling apart as soon
as the CPUs are brought online in a different order. For example, this
will happen because the operating system looks for such properties in the
CPU node it is trying to bring up, so that it can register a cooling
device.

Add such missing properties.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-28 16:41:35 +08:00