6358 Commits

Author SHA1 Message Date
Qingqing Zhuo
25879d7b49 drm/amd/display: Clean FPGA code in dc
[Why]
Drop dead code for Linux.

[How]
Remove all IS_FPGA_MAXIMUS_DC and IS_DIAG_DC

Reviewed-by: Ariel Bernstein <eric.bernstein@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 10:44:11 -04:00
Alvin Lee
7e60ab4eb3 drm/amd/display: Apply 60us prefetch for DCFCLK <= 300Mhz
[Description]
- Previously we wanted to apply extra 60us of prefetch for min DCFCLK
  (200Mhz), but DCFCLK can be calculated to be 201Mhz which underflows
  also without the extra prefetch
- Instead, apply the the extra 60us prefetch for any DCFCLK freq <=
  300Mhz

Reviewed-by: Nevenko Stupar <nevenko.stupar@amd.com>
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 10:44:08 -04:00
Daniel Miess
de231189e7 drm/amd/display: Fix possible underflow for displays with large vblank
[Why]
Underflow observed when using a display with a large vblank region
and low refresh rate

[How]
Simplify calculation of vblank_nom

Increase value for VBlankNomDefaultUS to 800us

Fixed a null pointer from previous commit of this change

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 10:44:05 -04:00
Daniel Miess
c02b04633c drm/amd/display: Revert vblank change that causes null pointer crash
Revert commit 1a4bcdbea431 ("drm/amd/display: Fix possible underflow for displays with large vblank")
Because it cause some regression

Fixes: 1a4bcdbea431 ("drm/amd/display: Fix possible underflow for displays with large vblank")
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 10:43:01 -04:00
Saaem Rizvi
3e8d74cb12 drm/amd/display: Trigger DIO FIFO resync on commit streams
[WHY]
Currently, there is an intermittent issue where a screen can either go
blank or be corrupted.

[HOW]
To resolve the issue we trigger the ramping logic for DIO FIFO so that
it goes back up to the correct speed.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Saaem Rizvi <syedsaaem.rizvi@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 10:42:58 -04:00
Dmytro Laktyushkin
0ab720d506 drm/amd/display: fix dcn315 pixel rate crb scaling check
fix dcn315 pixel rate crb scaling check error

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 10:42:43 -04:00
Hersen Wu
38ff516bb0 drm/amd/display: lower dp link training message level
[Why] some test apps report dp link training waring even dp
training pass. there are 4 tries of lt within
perform_link_training_with_retries. if lt pass within 4 tries,
it will NOT be reated as lt failure. for each try of lt, if lt
fails, current driver implementation prints message at warning
level. this let people think dp lt does not work properly.

[How] for 1st, 2nd and 3rd try of lt, print message at debug
level. for the 4th try of lt, print message at warning level.

Reviewed-by: Jerry Zuo <jerry.zuo@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 10:42:39 -04:00
Nicholas Kazlauskas
6812d74803 drm/amd/display: Update SR watermarks for DCN314
[Why & How]
Update parameters for SR watermarks for DCN314

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 10:42:30 -04:00
Dmytro Laktyushkin
7558922637 drm/amd/display: disable dcn315 pixel rate crb when scaling
The rough calculation does not account for scaling. Also, make 2
segments the minimum allowed per surface to avoid potential 0 detile
with mpc/odm combine on such outputs.

Reviewed-by: Ariel Bernstein <eric.bernstein@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 10:42:27 -04:00
Cruise Hung
f36f2648f3 drm/amd/display: Fix DMUB debugging print issue
[Why]
The DMUB diagnostic data was not printed out correctly.

[How]
Print the DMUB diagnostic data line by line.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Cruise Hung <cruise.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 10:42:24 -04:00
Hamza Mahfooz
fd73c85076 drm/amd/display: drop unused function set_abm_event()
set_abm_event() is never actually used. So, drop it.

Fixes: b8fe56375f78 ("drm/amd/display: Refactor ABM feature")
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Tom Rix <trix@redhat.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 10:38:52 -04:00
Hamza Mahfooz
48dd83c0fb drm/amd/display: drop redundant memset() in get_available_dsc_slices()
get_available_dsc_slices() returns the number of indices set, and all of
the users of get_available_dsc_slices() don't cross the returned bound
when iterating over available_slices[]. So, the memset() in
get_available_dsc_slices() is redundant and can be dropped.

Fixes: 97bda0322b8a ("drm/amd/display: Add DSC support for Navi (v2)")
Reported-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 10:38:37 -04:00
Aric Cyr
629b8ede8b drm/amd/display: 3.2.236
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:40:01 -04:00
Daniel Miess
3a31e8b89b drm/amd/display: Remove v_startup workaround for dcn3+
[Why]
Calls to dcn20_adjust_freesync_v_startup are no longer
needed as of dcn3+ and can cause underflow in some cases

[How]
Move calls to dcn20_adjust_freesync_v_startup up into
validate_bandwidth for dcn2.x

Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:39:58 -04:00
Rodrigo Siqueira
50a32b8cf4 drm/amd/display: Remove unnecessary variable
There is no need to use dc_version in the dc_construct_ctx since this
value is copied to dc_ctx->dce_version later. This commit removes the
extra steps.

Reviewed-by: Alex Hung <alex.hung@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:39:53 -04:00
Alvin Lee
fe9fa3859b drm/amd/display: Make unbounded req update separate from dlg/ttu
[Description]
- Updates to unbounded requesting should not be conditional
  on updates to dlg / ttu, as this could prevent unbounded
  requesting from being updated if dlg / ttu does not change

Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:39:49 -04:00
Leo (Hanghong) Ma
d205a800a6 drm/amd/display: Add visual confirm color support for MCLK switch
[Why && How]
We would like to have visual confirm color support for MCLK switch.
	1. Set visual confirm color to yellow: Vblank MCLK switch.
	2. Set visual confirm color to cyan: FPO + Vblank MCLK
	switch.
	3. Set visual confirm color to pink: Vactive MCLK switch.

Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:39:46 -04:00
Daniel Miess
1a4bcdbea4 drm/amd/display: Fix possible underflow for displays with large vblank
[Why]
Underflow observed when using a display with a large vblank region
and low refresh rate

[How]
Simplify calculation of vblank_nom

Increase value for VBlankNomDefaultUS to 800us

Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:39:44 -04:00
Rodrigo Siqueira
9c384ee8f9 drm/amd/display: Convert connector signal id to string
To improve the readability of the of the log, this commit introduces a
function that converts the signal type id to a human-readable string.

Reviewed-by: Jerry Zuo <jerry.zuo@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:39:41 -04:00
Alvin Lee
6ba5a269cd drm/amd/display: Update vactive margin and max vblank for fpo + vactive
[Description]
- Some 1920x1080@60hz displays have VBLANK time > 600us which we
  still want to accept for FPO + Vactive configs based on testing
	- Increase max VBLANK time to 1000us to allow these configs
	  for FPO + Vactive
- Increase minimum vactive switch margin for FPO + Vactive to 200us
	- Based on testing, 1920x1080@120hz can have a switch margin
	  of ~160us which requires significantly longer FPO stretch
	  margin (5ms) which we don't want to accept for now
- Also move margins into debug option

Reviewed-by: Jun Lei <jun.lei@amd.com>
Reviewed-by: Nevenko Stupar <nevenko.stupar@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:39:38 -04:00
Alvin Lee
1d8355ad92 drm/amd/display: Only skip update for DCFCLK, UCLK, FCLK on overclock
[Description]
- Update clocks is skipped in the GPU overclock sequence
- However, we still need to update DISPCLK, DPPCLK, and DTBCLK
  because the GPU overclock sequence could temporarily disable
  ODM 2:1 combine because we disable all planes in the sequence

Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:39:35 -04:00
Mustapha Ghaddar
f182239212 drm/amd/display: enable dpia validate
Use dpia_validate_usb4_bw() function

Fixes: a8b537605e22 ("drm/amd/display: Add function pointer for validate bw usb4")
Reviewed-by: Roman Li <roman.li@amd.com>
Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Mustapha Ghaddar <mghaddar@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:39:22 -04:00
Jiapeng Chong
e84e40dcb3 drm/amd/display: Simplify the calculation of variables
./drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c:586:37-39: WARNING !A || A && B is equivalent to !A || B.
./drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c:595:37-39: WARNING !A || A && B is equivalent to !A || B.

Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=4941
Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:38:57 -04:00
Huacai Chen
9a06655e73 drm/amdgpu/display: Enable DC_FP for LoongArch
LoongArch now provides kernel_fpu_begin() and kernel_fpu_end() that are
used like the x86 counterparts in commit 2b3bd32ea3a22ea2d ("LoongArch:
Provide kernel fpu functions"), so we can enable DC_FP on LoongArch for
supporting more DCN devices.

Signed-off-by: WANG Xuerui <kernel@xen0n.name>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:36:48 -04:00
Aric Cyr
aaa07c0d08 drm/amd/display: Promote DAL to 3.2.235
This version brings along following fixes:
- Block SubVP on displays that have pixclk > 1800Mhz
- Block SubVP high refresh when VRR active fixed
- Enforce 60us prefetch for 200Mhz DCFCLK modes
- Check Vactive for VRR active for FPO + Vactive
- Add symclk workaround during disable link output
- Show the DCN/DCE version in the log
- Add additional pstate registers to HW state query

Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:36:27 -04:00
Alvin Lee
807a1c1427 drm/amd/display: Block SubVP on displays that have pixclk > 1800Mhz
[Description]
- Enabling SubVP on high refresh rate displays had a side effect
  of also enabling on high bandwidth displays such as 8K60
- However, these are not validated and should be blocked for
  the time being
- Block SubVP on displays that have pix rate > 1800Mhz (includes
  8K60 displays)

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:35:11 -04:00
Alvin Lee
a00e595207 drm/amd/display: Block SubVP high refresh when VRR active fixed
[Description]
- SubVP high refresh is blocked when VRR is active variable, but
  we should also block it for when VRR is active fixed (video use
  case)

Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:35:07 -04:00
Alvin Lee
84f14428b1 drm/amd/display: Enforce 60us prefetch for 200Mhz DCFCLK modes
[Description]
- Due to bandwidth / arbitration issues at 200Mhz DCFCLK,
  we want to enforce minimum 60us of prefetch to avoid
  intermittent underflow issues
- Since 60us prefetch is already enforced for UCLK DPM0,
  and many DCFCLK's > 200Mhz are mapped to UCLK DPM1, in
  theory there should not be any UCLK DPM regressions by
  enforcing greater prefetch

Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:35:02 -04:00
Alvin Lee
62cc621604 drm/amd/display: Check Vactive for VRR active for FPO + Vactive
[Description]
- For FPO + Vactive cases, we rely on the Vactive display to be at
  it's nominal refresh rate because the Vactive pipe may not necessarily
  assert P-State allow while it's in VBLANK
- For cases where the Vactive display has a stretched VBLANK due to
  VRR, we could underflow when trying to complete an FPO + Vactive
  MCLK switch because the FPO display has limited VBLANK time in
  waiting for the Vactive display to assert P-State allow naturally
- Block FPO + Vactive if the Vactive display has VRR active (variable
  or fixed)

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:34:57 -04:00
Leo Chen
273f479977 drm/amd/display: Add symclk workaround during disable link output
[Why & How]
This is originally a change (9c75891f) in DCN32 because of the lack
of interface to set TX while keeping symclk on. Adding this workaround
to DCN314 will resolve the current issue.

Fixes: 9c75891feef0 ("drm/amd/display: rework recent update PHY state commit")
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Leo Chen <sancchen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:34:42 -04:00
Rodrigo Siqueira
bf7fda0b37 drm/amd/display: Show the DCN/DCE version in the log
Some times people send their dmesg log for debugging, and one common
task is to check the modesetting line to catch which DCN/DCE we need to
debug. This commit introduces a simple conversion from the DCN/DCE
version to a string shown in the dmesg log.

Reviewed-by: Hamza Mahfooz <Hamza.Mahfooz@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:34:09 -04:00
Sung Lee
738b3469f8 drm/amd/display: Add additional pstate registers to HW state query
[WHY]
These registers would be useful to know when debugging pstate issues.

[HOW]
Add additional registers to hw state query.

Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Sung Lee <sunglee@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:33:55 -04:00
Mario Limonciello
5a0510d58b drm/amd: Downgrade message about watermarks table after s0i3 to debug
This message shows up on s0i3 resume for DCN31 and DCN314 platforms but
it has been decided that this flow won't be changed and the message is
expected behavior.

Downgrade the message to debug.

Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:28:46 -04:00
Aric Cyr
4ab9d5848c drm/amd/display: 3.2.234
This version brings along following fixes:
- FW Release 0.0.165.0
- Add w/a to disable DP dual mode on certain ports
- Revert "Update scaler recout data for visual confirm"
- Filter out invalid bits in pipe_fuses
- Adding debug option to override Z8 watermark values
- Change default Z8 watermark values
- Workaround wrong HDR colorimetry with some receivers

Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:28:26 -04:00
George Shen
124155c0bd drm/amd/display: Add w/a to disable DP dual mode on certain ports
[Why]
Certain ports on DCN3.2 configs do not properly populate the BIOS
info table flag to indicate DP dual mode is unsupported.

[How]
Add a workaround to disable DP dual mode on the ports with the missing
BIOS info table flag.

Reviewed-by: Michael Strauss <Michael.Strauss@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:28:20 -04:00
Leo Ma
029c85adcc drm/amd/display: revert "Update scaler recout data for visual confirm"
This reverts commit 1068e987ad0be83a109147fe7fa0891700e8d80e.

A regression is found on this change, so revert it for the time being
and resubmit when issue is fixed.

Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Leo Ma <hanghong.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:27:50 -04:00
Samson Tam
f835a571ec drm/amd/display: filter out invalid bits in pipe_fuses
[Why]
Reading pipe_fuses from register may have invalid bits set, which may
 affect the num_pipes erroneously.

[How]
Add read_pipes_fuses() call and filter bits based on expected number
 of pipes.

Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:27:45 -04:00
Leo Chen
4dfa60aede drm/amd/display: Adding debug option to override Z8 watermark values
[Why & How]
Adding debug options to override Z8 watermark values for testing purposes.

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Leo Chen <sancchen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:27:42 -04:00
Leo Chen
9749a42db7 drm/amd/display: Change default Z8 watermark values
[Why & How]
Previous Z8 watermark values were causing flickering and OTC underflow.
Updating Z8 watermark values based on the measurement.

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Leo Chen <sancchen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:27:33 -04:00
Ilya Bakoulin
5b7bee5b44 drm/amd/display: Workaround wrong HDR colorimetry with some receivers
[Why]
Some scalers do not pick up color space updates unless the DP link
is disabled/re-enabled which can result in incorrect/washed out
HDR colors in some cases.

[How]
Call set_dpms_on to disable the link, re-train and re-enable with the
updated output color space.

Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:27:26 -04:00
Srinivasan Shanmugam
9ab367f838 drm/amd/display: Add logging when DP link training Channel EQ is Successful
Log when Channel Equalization is successful.

Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Fangzhi Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:27:14 -04:00
Srinivasan Shanmugam
9420a03406 drm/amd/display: Add logging for eDP v1.4 supported sink rates
Include eDP v1.4 panels supported sink rates in debug output,
useful info for knowing optimized link rates

Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Jerry Zuo <jerry.zuo@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:26:39 -04:00
Harshit Mogalapalli
44407010ce drm/amd/display: Fix possible NULL dereference in dc_dmub_srv_cmd_run_list()
We have a NULL check for 'dc_dmub_srv' in dc_dmub_srv_cmd_run_list()
but we are dereferencing it before checking.

Fix this moving the dereference next to NULL check.

This issue is found with Smatch(static analysis tool).

Fixes: e97cc04fe0fb ("drm/amd/display: refactor dmub commands into single function")
Signed-off-by: Harshit Mogalapalli <harshit.m.mogalapalli@oracle.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:25:59 -04:00
Tom Rix
b94f1cc93d drm/amd/display: return status of dmub_srv_get_fw_boot_status
gcc with W=1 reports
drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c:
  In function ‘dc_dmub_srv_optimized_init_done’:
drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c:184:26:
  error: variable ‘dmub’ set but not used [-Werror=unused-but-set-variable]
  184 |         struct dmub_srv *dmub;
      |                          ^~~~

The return status is never set.
It looks like a call to dmub_srv_get_fw_boot_status is missing.

Fixes: 499e4b1c722e ("drm/amd/display: add mechanism to skip DCN init")
Signed-off-by: Tom Rix <trix@redhat.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:23:23 -04:00
Srinivasan Shanmugam
27e6be5d75 drm/amd/display: DSC passthrough is for DP-HDMI pcon (SST pcon)
if check over DSC passthrough is removed, as this is not for
MST use case. It is for DP-HDMI pcon use case. sst pcon is
detected as sst not mst. In sst pcon dsc passthrough message
will not get below log printed

Fixes: 9b035d089086 ("drm/amd/display: Check & log if receiver supports MST, DSC & FEC.")
Suggested-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:21:49 -04:00
Christophe JAILLET
bafc31166a drm/amd/display: Fix a test dml32_rq_dlg_get_rq_reg()
It is likely p1_min_meta_chunk_bytes was expected here, instead of
min_meta_chunk_bytes.

Test the correct variable.

Fixes: dda4fb85e433 ("drm/amd/display: DML changes for DCN32/321")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:20:40 -04:00
Christophe JAILLET
960e27a574 drm/amd/display: Fix a test CalculatePrefetchSchedule()
It is likely Height was expected here, instead of Width.

Test the correct variable.

Fixes: 17529ea2acfa ("drm/amd/display: Optimizations for DML math")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:20:31 -04:00
Tom Rix
e94c25567c drm/amd/display: remove unused variables dispclk_delay_subtotal and dout
clang with W=1 reports
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.c:1003:15:
  error: variable 'dispclk_delay_subtotal' set but not used [-Werror,-Wunused-but-set-variable]
        unsigned int dispclk_delay_subtotal;
                     ^
This variable is not used, so remove it.
Which made dout unused, so also remove.

Signed-off-by: Tom Rix <trix@redhat.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 09:20:08 -04:00
Alvin Lee
b504f99cca drm/amd/display: Enforce 60us prefetch for 200Mhz DCFCLK modes
[Description]
- Due to bandwidth / arbitration issues at 200Mhz DCFCLK,
  we want to enforce minimum 60us of prefetch to avoid
  intermittent underflow issues
- Since 60us prefetch is already enforced for UCLK DPM0,
  and many DCFCLK's > 200Mhz are mapped to UCLK DPM1, in
  theory there should not be any UCLK DPM regressions by
  enforcing greater prefetch

Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-05-11 01:08:25 -04:00
Leo Chen
f57fa0f23d drm/amd/display: Add symclk workaround during disable link output
[Why & How]
This is originally a change (9c75891f) in DCN32 because of the lack
of interface to set TX while keeping symclk on. Adding this workaround
to DCN314 will resolve the current issue.

Fixes: 9c75891feef0 ("drm/amd/display: rework recent update PHY state commit")
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Leo Chen <sancchen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-05-11 01:08:00 -04:00