IF YOU WOULD LIKE TO GET AN ACCOUNT, please write an
email to Administrator. User accounts are meant only to access repo
and report issues and/or generate pull requests.
This is a purpose-specific Git hosting for
BaseALT
projects. Thank you for your understanding!
Только зарегистрированные пользователи имеют доступ к сервису!
Для получения аккаунта, обратитесь к администратору.
The newly added zx platform causes a build error when
CONFIG_THUMB2_KERNEL is enabled:
arch/arm/mach-zx/headsmp.S:16: Error: invalid immediate for address calculation (value = 0x00000004)
I'm assuming that the ROM code that is calling these entry
points runs in ARM mode, so there would be another problem
in the same file, and we can solve both problems at once
by adding a '.arm' statement that will make zx_resume_jump
and zx_secondary_startup both be built as ARM code.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Jun Nie <jun.nie@linaro.org>
Tested-by: Jun Nie <jun.nie@linaro.org>
to making omap1 support multiarch. After this series we still need to
make omap1 use the common clock framework and fix up the drivers to not
rely on includes from mach and plat directories.
Note that this branch depends on a GPIO driver fix in v4.1-rc3
d2d05c65c40e ("gpio: omap: Fix regression for MPUIO interrupts").
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVXlPnAAoJEBvUPslcq6Vzb3UP/2ObsLBggAG9uAFkTV4Jg4Sy
BKuetmnLpnthbjLXBXgvErdJwDGVjiB9DzhOe9x3kkqM8+emRW/ZS/wBdNNarGiY
qJo0y6aCgYOxYbELpgksfQfoPGEdU7aAauo7pIneDXHwxFwpcxlCRZc3QVLZRqPO
M85THI0h699Ejs+rjIyJD/juGb1O5HKk2qJa0yGn/MNnTeh6OVDFOU7oK95tB5WF
DiHJl/rQouQqERPrteM1iFqO9BV7F0K0bRrLC764YyvzG7uEb41f8TNOWFGnABDV
abHiAL6ZvYrfkFZK9Y29pCJriZjOerVbP4yjEHlORiu5Jng6i0Jmw+Jk67FakwAl
6IfwLItpmZtq0GjsvR7eeyfu8NF2Lk0HGFDuG2kSnRzsihjnJnF+ZFNejmg2b8e4
Rwuq6rU9MZQhe9uzJkArhVP5JZns8V2H7kFuep0/N1pUeGoQqJsGjaCQIcqoVvhl
Sub02jBFrvby3gS+fUSwjdbLRweD/iUrzAMBqnPNyB1z9OUxjeBU5k2YJM0yRWCi
tPTEoGXu75qCJguIH3bbQg7QY/g/eqYZVRTVGO1h2PRlLwEy5lnt9aS66BPn3rJj
tlYWuqq6vhnQrZBGadIHI5KHIB+eVU37hKmzv9NuD2J2fWXG/gTxqJPZWHuGT96f
p0VZTqHG2CkQO0LL58hf
=FVxF
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.2/omap1-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
Merge fixed up omap1 sparse irq support for v4.2 from Tony Lindgren:
Add support for CONFIG_SPARSE_IRQ for omap1. This takes us a bit closer
to making omap1 support multiarch. After this series we still need to
make omap1 use the common clock framework and fix up the drivers to not
rely on includes from mach and plat directories.
Note that this branch depends on a GPIO driver fix in v4.1-rc3
d2d05c65c40e ("gpio: omap: Fix regression for MPUIO interrupts").
* tag 'omap-for-v4.2/omap1-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP1: Fix section mismatch warnings for omap_cfg_reg
ARM: OMAP1: Fix randconfig builds if ARCH_OMAP15XX not selected
ARM: OMAP1: Change interrupt numbering for sparse IRQ
ARM: omap1: Switch to use MULTI_IRQ
ARM: OMAP1: Switch to use generic irqchip in preparation for sparse IRQ
ARM: OMAP1: Move UART defines to prepare for sparse IRQ
Merge mach-bcm changes from Florian Fainelli:
This pull request contains the following changes:
- Rafal adds an additional fault code to be ignored by the kernel on BCM5301X SoC
- BCM63138 SMP support which:
* common code to control the PMB bus, to be shared with a reset
controller driver in drivers/reset
* secondary CPU initialization sequence using PMB helpers
* small changes suggested by Russell King to allow platforms to disable VFP
* tag 'arm-soc/for-4.2/soc-take2' of http://github.com/broadcom/stblinux:
ARM: BCM63xx: Add SMP support for BCM63138
ARM: vfp: Add vfp_disable for problematic platforms
ARM: vfp: Add include guards
ARM: BCM63xx: Add secondary CPU PMB initialization sequence
ARM: BCM63xx: Add Broadcom BCM63xx PMB controller helpers
ARM: BCM5301X: Ignore another (BCM4709 specific) fault code
This is cleary used after init time too for example for
configuring UART wake-up events during runtime. This fixes
section mismatch warnings for randconfig builds that happen
because __init_or_module.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the omap1 SPARSE_IRQ changes mach/irqs.h is no longer
automatically included. Turns out now we rely on ARCH_OMAP15XX
including hardware.h from memory.h, so without ARCH_OMAP15XX
we get build failures.
As we have legacy drivers still relying on these indirect
includes, let's not add more mach includes to the drivers.
Those have to be removed anyways for multiplatform support.
Let's fix up mach-omap1 to include soc.h where cpu_is_omap
checks are done, and common.h for board-*.c files.
But let's keep the indirect memory.h include for now to avoid
unnecessary churn in the drivers.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add support for booting the secondary CPU on BCM63138, this involves:
- locating the bootlut to write the reset vector
- powering up the second CPU when we need to using the DT-supplied PMB
references
- disabling VFP when enabled such that we can keep having SMP
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Some platforms might not be able to fully utilize VFP when e.g: one CPU
out of two in a SMP complex lacks a VFP unit. Adding code to migrate
task to the CPU which has a VFP unit would be cumbersome and not
performant, instead, just add the ability to disable VFP.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The sequence to initialize a secondary CPU using the BCM63138 PMB is
extremely specific and represents much more code than any other on-chip
peripheral (AHCI, USB 3.0 or integrated Ethernet switch), as such we
keep that code local and utilize Device Tree to lookup all the resources
we need from the CPU device tree node.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This patch adds both common register definitions and helper functions
used to issue read/write commands to the Broadcom BCM63xx PMB controller
which is used to power on and release from reset internal on-chip
peripherals such as the integrated Ethernet switch, AHCI, USB, as well
as the secondary CPU core.
This is going to be utilized by the BCM63138 SMP code, as well as by the
BCM63138 reset controller later.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This patch allows to build the Kernel for Vybrid (VF6xx) SoC
when ARMv7-M CPU is selected. The resulting image runs on the
secondary Cortex-M4 core. This core has equally access to all
peripherals as the main Cortex-A5 core. However, there is no
resource control mechanism, hence when both cores are used
simultaneously, orthogonal device tree's are required.
The boot CPU is dependent on the SoC variant. The available
boards use mostly variants where the Cortex-A5 is the primary
and hence the boot CPU. Booting the secondary Cortex-M4 CPU
needs SoC specific registers written. There is no in kernel
support for this right now, a external userspace utility
called "m4boot" can be used to boot the kernel:
m4boot xipImage initramfs.cpio.lzo vf610m4-colibri.dtb
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This introduces a new top level config symbol ARM_SINGLE_ARMV7M
for non-MMU, ARMv7-M platforms. It also support multiple ARMv7-M
platforms in one kernel image since the cores share the same
basic memory layout and interrupt controller. However, this works
only if the combined platforms also have a similar (main) memory
layout.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Remove the needless differences between MMU/!MMU addruart calls.
This allows to use the same addruart macro on SoC level. Useful
for SoC consisting of multiple CPUs with and without MMU such as
Freescale Vybrid.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Broadcom ARM devices seem to generate some fault once per boot. We
already have an ignoring handler for BCM4707/BCM4708, but BCM4709
generates different code.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This pull request for the MAINTAINERS file contains the following changes:
- Brian adds a general "brcmstb" regexp to catch Broadcom Set Top Box related
changes throughout the Linux tree
* tag 'arm-soc/for-4.2/maintainers' of http://github.com/broadcom/stblinux:
MAINTAINERS: add brcmstb regex
Change interrupt numbering for sparse IRQ. We do this using
a fixed offset until we can drop irqs.h once all it's users
have been updated.
Note that this depends on the GPIO fix for the MPUIO IRQs
"gpio: omap: Fix regression for MPUIO interrupts".
Also note that this patch adds some extra irq alloc warnings
that will go away when we stop calling irq_alloc_descs
in gpio-omap.c with a follow-up patch.
Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This allows us to get a bit further with SPARSE_IRQ and
MULTIARCH support.
Note that we now also rename omap_irq_flags to omap_l2_irq
as that's the omap_irq_flags naming is confusing. It just
contains the interrupt number for the l2 irq.
Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Let's set up things ready for enabling sparse IRQ and remove the
omap_read/write usage.
Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Tony Lindgren <tony@atomide.com>
These have been indirectly included via asm/irqs.h that
has included mach/hardware.h unless SPARSE_IRQ is specified.
Let's move them to where the other OMAP serial defines for
8250 are.
Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This makes uniphier behave like all the other platforms that
support TWD, and only select this driver when SMP is enabled.
Without this, we get a compile error on UP builds:
arch/arm/kernel/smp_twd.c: In function 'twd_local_timer_of_register':
arch/arm/kernel/smp_twd.c:391:20: error: 'setup_max_cpus' undeclared (first use in this function)
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Using a dedicated symbol for low-level debugging instead of the
arch symbol will make this platform play nice when enabled on a
kernel that supports multiple platforms.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add a MAINTAINER entry covering all NXP LPC18xx/43xx
machine and drivers files.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The SLCR is unconditionally unlocked early on boot in zynq_slcr_init()
and not ever re-locked. As such, it is not necessary to explicitly unlock in
the restart codepath.
Signed-off-by: Josh Cartwright <joshc@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
By making use of the restart_handler chain mechanism, the SLCR-based
reset mechanism can be prioritized amongst other mechanisms available on
a particular board.
Choose a default high-ish priority of 192 for this restart mechanism.
Signed-off-by: Josh Cartwright <joshc@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add a MAINTAINER entry covering all STM32 machine and drivers files.
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Bring up the secondary core. Enable hotplug with supporting
powering off secondary core.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Use the UART0 peripheral for low level debug. Only the UART port 0 is
currently supported.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add basic code for ZTE ZX296702 platform.
[arnd: removed unused zx296702_init_machine function, and changed
l2c aux val to default]
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add support for NXP's LPC18xx (Cortex-M3) and LPC43xx (Cortex-M4)
SoCs. These SoCs are NXP's high preformance MCU line and can run at
clock speeds up to 180 MHz for LPC18xx and 204 MHz for LPC43xx.
LPC43xx is more or less a LPC18xx with a Cortex-M4F core and a few
extra peripherals. The LPC43xx series also features one or two
Cortex-M0 cores that can be used to offload the main M4 core.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
STMicrolectronics's STM32 series is a family of Cortex-M
microcontrollers. It is used in various applications, and
proposes a wide range of peripherals.
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The main and only feature is the conversion of all pxa variants to clock
framework. This encompasses pxa25x, pxa27x and pxa3xx, for all boards.
This should be a disruptive cycle in the normally quiet pxa history, as
the change can break any platform, and the test were performed on only 4
boards (lubbock, zylonite, mioa701, cm-x300).
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVU6BbAAoJEAP2et0duMsSBYYP/14D6mb8ayh9Arz4ewfihGBF
7utbgdTHCJqhkAMVOgbBqogokrhLXdz/D7p2wWPE5CndDfyyGLhynzI0ZK3yLlTk
GSIN99F/OsIpfZ4PpnZeWYe7YvMo3b6cB1uu0qCqLyxky/P8bu2zhTip15IKUWyq
V5WLOpFVGX1FALkLqK0fzg9nwJnbojXRyDdgsAOhZVdTqr7jLR4O/e0RSPZIokBU
tQ6gR/QnlHktTCIN5dVBatiTQDJrTR7sRvEfPfKCSaiC86QfCbiQZ2wXJp32rIvT
kOrfBunvH6y1etgZXiAczwCWnQ2GmvG44i/HQ9wKQsBFrrXveuI18Z9CJTl3MKrO
lDsD0sYZ1F0ufykfKCDgRZobhIdtoBG5jv3MLP7ZV1o07weWdtj+yy3Mb72ULX5I
c0EjgWfx6KqqT1gYTNOgrarM+WJe00aqQlGP39AIzpcp9AwyrjuchvXb6kabKWo1
wgPxtNw3I012qkPJ3ve/hi2Wwt7nfCst52r9l8ZKo/xHpbQ/HhUY/RciYygNMFsz
7R4NqKhbYQvLjDQY8sCbgWxj8Q3loT54zqSDDUqXZAf/oLmxjafEHtbIr5nXxevk
jygV+OSZwXDG7LXuJmFtYqsyWYU7Ow33BMyfWFJKuS1eJC/ZRDnkQUxLqCfkQiRC
bIwbdTkKFrDHvyttbMn0
=Gv7n
-----END PGP SIGNATURE-----
Merge tag 'pxa-for-4.2' of https://github.com/rjarzmik/linux into next/soc
Merge "pxa changes for v4.2 cycle" from Robert Jarzmik:
The main and only feature is the conversion of all pxa variants to clock
framework. This encompasses pxa25x, pxa27x and pxa3xx, for all boards.
This should be a disruptive cycle in the normally quiet pxa history, as
the change can break any platform, and the test were performed on only 4
boards (lubbock, zylonite, mioa701, cm-x300).
* tag 'pxa-for-4.2' of https://github.com/rjarzmik/linux:
ARM: pxa: Constify irq_domain_ops
ARM: pxa: Transition pxa25x, pxa27x, pxa3xx to clk framework
ARM: pxa: convert eseries to clock framework
ARM: pxa: Transition pxa25x and pxa27x to clk framework
ARM: pxa: pxa27x skip default device initialization with DT
clk: pxa: add missing pxa27x clocks for Irda and sa1100-rtc
ARM: pxa: move gpio11 clock to board files
ARM: pxa: change clocks init sequence
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVVGbzAAoJEFGvii+H/HdhXnsP/ihOP9xB24jBHgEWsZ9PaekZ
YePv9Gxsxc9CvHIUJlWnwbvF/+Th+2Z2q2b2cAFjQutreEPYyi1g4HkhkVn/aXG7
VgkBhdeSFwWX/VZAun/r3wZdzfzMKOHphoyejKAClAPSM2lQAYCdxCx+wzEFMMNv
HtIeUCtpRaR+eycqkLMobhO0PO4BW4eIo8+F3cDHcAmR5q7MTmoHyFa9l/V/WjfK
M0YV8a12m/8itfItzisloaFgMWOpxS6/8sUI7EEbD3dUK7XfCr0+rpzJ/ALNHrKr
3V7StS1XOLxa7F1dKoi10r7SxSxaeXxmKTU84Y9YZSImeNBNdvtYs0E198jgA0mN
OUkkd/6InhM3+5OCnNmwH2GAhQKbem+5lZgUu5W7hG3fyO1mMjZW7IxiqXgj4nGu
6jlT5evdPTuvTw+1n5dC6AJtUrI40YRZDadtNLXBq/LqEsyO0+EcmVQlrsSTzrxS
rxbSayXEQbwzL18L0iPC0KAFNm62VlG1eOcbdaFU2H0WK8wKimm+Hj9m9SkResfp
npNT/bgLuuW+hUeuWAbzmqSuLxreWTFvt2N5801vdtG/tnX3nO9lNUYQH7Zj8u7s
qZN391m6W5Mr+N6cMqMxKIFe+4Ea9o5eUmOX7g8KvGAzapRfOLdoPo3wR5vA04s3
FEmDv7Ah4T2SpexAKq8U
=TUcB
-----END PGP SIGNATURE-----
Merge tag 'rpi-soc-for-armsoc-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi into next/soc
Merge "RaspberryPi SoC (mach) changes due for v4.2" from Lee Jones:
* tag 'rpi-soc-for-armsoc-v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi:
ARM: bcm2835: Move the restart/power_off handling to the WDT driver
ARM: bcm2835: Drop the init_irq() hook
ARM: bcm2835: Skip doing our own iotable_init() initialization
Since the WDT is what's used to drive restart and power off, it makes
more sense to keep it there, where the regs are already mapped and
definitions for them provided. Note that this means you may need to
add CONFIG_BCM2835_WDT to retain functionality of your kernel.
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
This is the default function that gets called if the hook is NULL.
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
The only thing we were using this 16MB mapping of IO peripherals for
was the uart's early debug mapping. If we just drop the map_io hook,
the kernel will call debug_ll_io_init() for us, which maps the single
page needed for the device.
Signed-off-by: Eric Anholt <eric@anholt.net>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
This could probably consolidate a few file listings. And it satisfies
the spirit of the highly annoying [1] checkpatch warning for every new
file, though it sadly won't quash it.
[1] https://lkml.org/lkml/2014/12/17/24
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
A couple of changes to the core SoC support code. Perhaps the most
important part is a fix for a regression in LP1 suspend/resume code that
was introduced a while back.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJVU1HFAAoJEN0jrNd/PrOhZNQP/ji9c+i3NPHn8Ll1bd9G8ppB
Mv3SCjRqen1FVgrjuduGGlw+d6iJxVQvYM9tZ09ciFBLEsYzardiPpWeTau7stbn
AKehXQQLoaj8ZZDJta09aLSjwddm9OkYGfceRykPnRoSRNDiWxGA71KXiYTN3TxZ
A1mEJ7oIUZhZvltcriNeU9R/54/slLq00tPaD6XsH32l6GTdlS591mDgPBVia8TC
HkcbXhutHInXtaP0IAaWHYrS2hp0Gy5/bIabKgjmK1bd1tBgf8g3hxe1YkUIaeWf
j9F3Pb6SV54GSTV0p6hDsX/FnD7j9/ly3XQasdMp/+YOMCG+RfQjPhri2q32NIBm
QDeG7BYUQJ8ktAFuGgOiwxpp9plTUBSMDDYOraHSJf2FVqH2NTlLkm9vamm5d6wb
edlkyTmy5xeUCX4+hADgEbSTxSagXzSiZ4mLPtCL656ASwGriEg/HoyVnzHWNvJa
6il5eEg6qaTYh2Ui+4z6BYZx8DQ8tQ51sg9lW/Y+QL71jopAHqS3wjnKJ/RlcePQ
TD4tYhf6ALMLGZWGB/VYRwKPxYuI+owzf7P7mBzX0NtbY1PxsiQA2ximO7Y+XegE
Ou2rO2lQVofH3WbzhfYgT4/+c0NtDpdI2FGsEMhsPYE3zLTyO+d8gsEQsI6oGkrU
I/soe1xKK/4BZT6IZTP7
=BR2n
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-4.2-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc
Merge "ARM: tegra: Core SoC changes for v4.2-rc1" from Thierry Reding:
A couple of changes to the core SoC support code. Perhaps the most
important part is a fix for a regression in LP1 suspend/resume code that
was introduced a while back.
* tag 'tegra-for-4.2-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
soc/tegra: pmc: move to using a restart handler
ARM: tegra20: Store CPU "resettable" status in IRAM
soc/tegra: Watch wait_for_completion_timeout() return type
- Add big endian support
- Add earlyprintk support on UART1 that is used on Arria10
- Remove the need to map uart_io_desc
- Use of_iomap to map the SCU
- Remove socfpga_smp_init_cpus as arm_dt_init_cpu_maps is already doing
the CPU mapping.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJVU1X6AAoJEBmUBAuBoyj0ixoP/3l2MxAxQt+SRz70y3ceFqx+
IVbGpcDQdm7RohCFQVV7PVtpjm+RllYjjlRYWN/5/xfUEgjUgCiYlEPch+zFBDvA
u9jpK7EdXHUYjAYmlti+Rw4jXXsYy+DzkZeMm6t/MlSj61exKW9iRU+/cdhXDyLx
m81fGf+M8V/2xMIbHC6f/6xk2+a8WtTwCoh1FaCJLp+qkedQ4QOJPDjYSWBiubXH
g7ydcuIiBpOuc57E1rzFWHeJgQu9VO+hLrNrazrfN/awbonPEL7hMJR2+odrDzHw
wnwijqQCRDW1dZOAKNulH7h/9IzxjFyyIjdAbUF8ZplxIT0vtLbYPldd/435XJFX
9VCUzVfAc0Vu5sfl3InbcRNoJDkCPavqcug1pYJkJlE8TeHcV8ylC7uzhWWrIRWa
mzJq+j3p/E2pbvfv9YHccNaGRL4p9icN0eojM3fSwAlG9rAsDGFGNJH3Qb4tuwem
H3MyhrIr9eveVBSkvz71sPy+ZHRL7EcPVFggpyXG2kNptb/K1P6cdDBO+mfl7ymM
oVaKaGfpm3sCF9h/vLDWlsZUVF9eEsWO4qx5b0852T94WPkG+qg8p+MCYX2/7lGO
41nKAWZpKRQj/9LvQpxlPnZSUhqcOPuHVVgMCDaXbwN9tGo7hJuaHpq4abElH3Ha
h1lu5YGA9V0wf+zbK3S/
=60ig
-----END PGP SIGNATURE-----
Merge tag 'socfpga_updates_for_v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/soc
Merge "SoCFPGA updates for v4.2" from Dinh Nguyen:
- Add big endian support
- Add earlyprintk support on UART1 that is used on Arria10
- Remove the need to map uart_io_desc
- Use of_iomap to map the SCU
- Remove socfpga_smp_init_cpus as arm_dt_init_cpu_maps is already doing
the CPU mapping.
* tag 'socfpga_updates_for_v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: socfpga: use of_iomap to map the SCU
ARM: socfpga: remove the need to map uart_io_desc
ARM: socfpga: Add support for UART1 debug uart for earlyprintk
ARM: socfpga: support big endian for socfpga
ARM: socfpga: enable big endian for secondary core(s)
ARM: debug: fix big endian operation for 8250 word mode
Use of_iomap to map the "arm,cortex-a9-scu". By doing this, we can remove
map_io in socfpga.c.
Also, we can remove socfpga_smp_init_cpus, as arm_dt_init_cpu_maps is
already doing the CPU mapping.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
The irq_domain_ops are not modified by the driver and the irqdomain core
code accepts pointer to a const data.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Transition the PXA25x, PXA27x and PXA3xx CPUs to the clock framework.
This transition still enables legacy platforms to run without device
tree as before, ie relying on platform data encoded in board specific
files.
This is the last step of clock framework transition for pxa
platforms. It was tested on lubbock (pxa25x), mioa701 (pxa27x) and
zylonite (pxa3xx).
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
As pxa architecture transitions to clock framework, the previously
available INIT_CLKREG is no more. Use the fixed clock rate initializer
to declare the "fake" CLK_CK32K in eseries.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
