46372 Commits

Author SHA1 Message Date
Kuninori Morimoto
fed4be313a
ASoC: simple-card-utils.c: share asoc_graph_parse_dai()
Current Audio Graph Card/Card2 implements asoc_simple_parse_dai()
on each driver, but these are same function.
This patch share it as asoc_graph_parse_dai().

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87o7lihpvy.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-14 14:47:53 +01:00
Venkata Prasad Potturu
fd01a15164
ASoC: SOF: amd: Add support for IPC with a reply_size set to zero
Add support for IPC tx_message with a reply_size set to zero,
return zero when message reply_size is zero at acp_dsp_ipc_get_reply().

Signed-off-by: Venkata Prasad Potturu <venkataprasad.potturu@amd.com>
Link: https://lore.kernel.org/r/20230614103707.2246296-1-venkataprasad.potturu@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-14 12:27:00 +01:00
Mark Brown
22691a0513
ASoC: rt1318: Use maple tree register cache
The rt1318 can only support single register read and write operations
so does not benefit from block writes. This means it gets no benefit from
using the rbtree register cache over the maple tree register cache so
convert it to use maple trees instead, it is more modern.

Tested-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230609-asoc-rt-sdw-maple-v1-8-85ee50c93905@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-14 12:26:45 +01:00
Mark Brown
6179a2e84f
ASoC: rt1316: Use maple tree register cache
The rt1316 can only support single register read and write operations
so does not benefit from block writes. This means it gets no benefit from
using the rbtree register cache over the maple tree register cache so
convert it to use maple trees instead, it is more modern.

Tested-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230609-asoc-rt-sdw-maple-v1-7-85ee50c93905@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-14 12:26:44 +01:00
Mark Brown
4f69e29ace
ASoC: rt1308: Use maple tree register cache
The rt1308 can only support single register read and write operations
so does not benefit from block writes. This means it gets no benefit from
using the rbtree register cache over the maple tree register cache so
convert it to use maple trees instead, it is more modern.

Tested-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230609-asoc-rt-sdw-maple-v1-6-85ee50c93905@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-14 12:26:43 +01:00
Mark Brown
799457a320
ASoC: rt722: Use maple tree register cache
The rt722 can only support single register read and write operations so
does not benefit from block writes. This means it gets no benefit from
using the rbtree register cache over the maple tree register cache so
convert it to use maple trees instead, it is more modern.

Tested-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230609-asoc-rt-sdw-maple-v1-5-85ee50c93905@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-14 12:26:42 +01:00
Mark Brown
dd08b6ddcb
ASoC: rt715: Use maple tree register cache
The rt715 can only support single register read and write operations so
does not benefit from block writes. This means it gets no benefit from
using the rbtree register cache over the maple tree register cache so
convert it to use maple trees instead, it is more modern.

Tested-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230609-asoc-rt-sdw-maple-v1-4-85ee50c93905@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-14 12:26:41 +01:00
Mark Brown
f438c799aa
ASoC: rt712: Use maple tree register cache
The rt712 can only support single register read and write operations so
does not benefit from block writes. This means it gets no benefit from
using the rbtree register cache over the maple tree register cache so
convert it to use maple trees instead, it is more modern.

Tested-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230609-asoc-rt-sdw-maple-v1-3-85ee50c93905@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-14 12:26:41 +01:00
Mark Brown
0a57572933
ASoC: rt711: Use maple tree register cache
The rt711 can only support single register read and write operations so
does not benefit from block writes. This means it gets no benefit from
using the rbtree register cache over the maple tree register cache so
convert it to use maple trees instead, it is more modern.

Tested-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230609-asoc-rt-sdw-maple-v1-2-85ee50c93905@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-14 12:26:40 +01:00
Mark Brown
049a78048e
ASoC: rt700: Use maple tree register cache
The rt700 can only support single register read and write operations so
does not benefit from block writes. This means it gets no benefit from
using the rbtree register cache over the maple tree register cache so
convert it to use maple trees instead, it is more modern.

Tested-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230609-asoc-rt-sdw-maple-v1-1-85ee50c93905@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-14 12:26:39 +01:00
Stephen Boyd
3e253b2169 ASoC: tlv320aic32x4: pll: Remove impossible condition in clk_aic32x4_pll_determine_rate()
Smatch warns:

sound/soc/codecs/tlv320aic32x4-clk.c:219 clk_aic32x4_pll_determine_rate() warn: unsigned 'rate' is never less than zero.

Cc: Maxime Ripard <maxime@cerno.tech>
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202306101217.08CRVGcK-lkp@intel.com/
Fixes: 25d43ec352ea ("ASoC: tlv320aic32x4: pll: Switch to determine_rate")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20230613011201.1166753-1-sboyd@kernel.org
Reviewed-by: Maxime Ripard <mripard@kernel.org>
2023-06-13 12:00:55 -07:00
Mark Brown
a11e6515b0
ASoC: add new trigger ordering method
Merge series from Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>:

This patch-set adds new "trigger" starting/stopping method.
2023-06-13 17:39:51 +01:00
Mark Brown
e8181a895b
ASoC: add N cpus to M codecs dai link support
Merge series from Bard Liao <yung-chuan.liao@linux.intel.com>:

Currently, ASoC supports dailinks with the following mappings:
1 cpu DAI to N codec DAIs
N cpu DAIs to N codec DAIs
But the mapping between N cpu DAIs and M codec DAIs is not supported.
The reason is that we didn't have a mechanism to map cpu and codec DAIs

This series suggests a new snd_soc_dai_link_codec_ch_map struct in
struct snd_soc_dai_link{} which provides codec DAI to cpu DAI mapping
information used to implement N cpu DAIs to M codec DAIs support.

And add the codec_ch_maps to SOF SoundWire machine driver.
2023-06-13 17:16:51 +01:00
Mark Brown
1012bfdd2f
ASoC: Use maple tree for Cirrus Logic devices
Merge series from Mark Brown <broonie@kernel.org>:

A lot of the Cirrus Logic devices only support single register
read/write operations so they get no benefit from using the rbtree cache
over the more modern maple tree cache, convert them to use maple tree.
2023-06-13 17:16:44 +01:00
Juerg Haefliger
82a28d5aa5
ASoC: siu: Add MODULE_FIRMWARE macro
The module loads firmware so add a MODULE_FIRMWARE macro to provide that
information via modinfo.

Signed-off-by: Juerg Haefliger <juerg.haefliger@canonical.com>
Link: https://lore.kernel.org/r/20230613095454.38696-1-juerg.haefliger@canonical.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-13 12:15:12 +01:00
Kuninori Morimoto
099770e2da
ASoC: remove old trigger ordering method
All drivers switch to use generic trigger ordering method.
Let's remove old method.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87legufnyy.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-13 12:11:23 +01:00
Kuninori Morimoto
0a67a14f74
ASoC: starfive: use use new trigger ordering method
ASoC is now supporting generic trigger ordering method.
This patch switch to use it.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87mt1afnz5.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-13 12:11:22 +01:00
Kuninori Morimoto
38cb2a362d
ASoC: atmel: use use new trigger ordering method
ASoC is now supporting generic trigger ordering method.
This patch switch to use it.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Tested-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/87o7lqfnzb.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-13 12:11:21 +01:00
Kuninori Morimoto
4a6aeaebbe
ASoC: amd: use use new trigger ordering method
ASoC is now supporting generic trigger ordering method.
This patch switch to use it.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87pm66fnzi.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-13 12:11:20 +01:00
Kuninori Morimoto
356caf663d
ASoC: add new trigger ordering method
Current ASoC is assuming that trigger starting order is
Link -> Component -> DAI as default, and its reverse order for stopping.
But some Driver / Card want to reorder it for some reasons.
We have such flags, but is unbalance like below.

	struct snd_soc_component_driver	:: start_dma_last
	struct snd_soc_dai_link		:: stop_dma_first

We want to have more flexible, and more generic method.
This patch adds new snd_soc_trigger_order for start/stop at
component / DAI-link.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87r0qmfnzx.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-13 12:11:19 +01:00
Bard Liao
0281b02e19
ASoC: Intel: sof_sdw: add dai_link_codec_ch_map
The captured data will be combined from each cpu DAI if the dai link
has more than one cpu DAIs. We can set channel number indirectly by
adding sdw_codec_ch_maps.

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20230607031242.1032060-3-yung-chuan.liao@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-13 12:11:16 +01:00
Bard Liao
ac950278b0
ASoC: add N cpus to M codecs dai link support
Currently, ASoC supports dailinks with the following mappings:
1 cpu DAI to N codec DAIs
N cpu DAIs to N codec DAIs
But the mapping between N cpu DAIs and M codec DAIs is not supported.
The reason is that we didn't have a mechanism to map cpu and codec DAIs

This patch suggests a new snd_soc_dai_link_codec_ch_map struct in
struct snd_soc_dai_link{} which provides codec DAI to cpu DAI mapping
information used to implement N cpu DAIs to M codec DAIs
support.

When a dailink contains two or more cpu DAIs, we should set channel
number of cpus based on its channel mask. The new struct also provides
channel mask information for each codec and we can construct the cpu
channel mask by combining all codec channel masks which map to the cpu.

The N:M mapping is however restricted to the N <= M case due to physical
restrictions on a time-multiplexed bus such as I2S/TDM, AC97, SoundWire
and HDaudio.

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20230607031242.1032060-2-yung-chuan.liao@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-13 12:11:15 +01:00
Mark Brown
0eff26b13d
ASoC: cs35l30: Use maple tree register cache
The cs35l30 can only support single register read and write operations
so does not benefit from block writes. This means it gets no benefit from
using the rbtree register cache over the maple tree register cache so
convert it to use maple trees instead, it is more modern.

Acked-by: David Rhodes <david.rhodes@cirrus.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230609-asoc-cirrus-maple-v1-10-b806c4cbd1d4@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-13 12:11:08 +01:00
Mark Brown
ce598b2f83
ASoC: cs43130: Use maple tree register cache
The cs43130 can only support single register read and write operations
so does not benefit from block writes. This means it gets no benefit from
using the rbtree register cache over the maple tree register cache so
convert it to use maple trees instead, it is more modern.

Acked-by: David Rhodes <david.rhodes@cirrus.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230609-asoc-cirrus-maple-v1-9-b806c4cbd1d4@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-13 12:11:08 +01:00
Mark Brown
62145b0a53
ASoC: cs42l83: Use maple tree register cache
The cs42l83 can only support single register read and write operations
so does not benefit from block writes. This means it gets no benefit from
using the rbtree register cache over the maple tree register cache so
convert it to use maple trees instead, it is more modern.

Acked-by: David Rhodes <david.rhodes@cirrus.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230609-asoc-cirrus-maple-v1-8-b806c4cbd1d4@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-13 12:11:07 +01:00
Mark Brown
7e39a71876
ASoC: cs42l73: Use maple tree register cache
The cs42l73 can only support single register read and write operations
so does not benefit from block writes. This means it gets no benefit from
using the rbtree register cache over the maple tree register cache so
convert it to use maple trees instead, it is more modern.

Acked-by: David Rhodes <david.rhodes@cirrus.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230609-asoc-cirrus-maple-v1-7-b806c4cbd1d4@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-13 12:11:06 +01:00
Mark Brown
6b7fed83c9
ASoC: cs42l42: Use maple tree register cache
The cs42l42 can only support single register read and write operations
so does not benefit from block writes. This means it gets no benefit from
using the rbtree register cache over the maple tree register cache so
convert it to use maple trees instead, it is more modern.

Acked-by: David Rhodes <david.rhodes@cirrus.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230609-asoc-cirrus-maple-v1-6-b806c4cbd1d4@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-13 12:11:05 +01:00
Mark Brown
bb1bd25ad7
ASoC: cs4234: Use maple tree register cache
The cs4234 can only support single register read and write operations
so does not benefit from block writes. This means it gets no benefit from
using the rbtree register cache over the maple tree register cache so
convert it to use maple trees instead, it is more modern.

Acked-by: David Rhodes <david.rhodes@cirrus.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230609-asoc-cirrus-maple-v1-5-b806c4cbd1d4@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-13 12:11:04 +01:00
Mark Brown
28f851babc
ASoC: cs35l35: Use maple tree register cache
The cs35l35 can only support single register read and write operations
so does not benefit from block writes. This means it gets no benefit from
using the rbtree register cache over the maple tree register cache so
convert it to use maple trees instead, it is more modern.

Acked-by: David Rhodes <david.rhodes@cirrus.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230609-asoc-cirrus-maple-v1-4-b806c4cbd1d4@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-13 12:11:03 +01:00
Mark Brown
e7795f2d29
ASoC: cs35l34: Use maple tree register cache
The cs35l34 can only support single register read and write operations
so does not benefit from block writes. This means it gets no benefit from
using the rbtree register cache over the maple tree register cache so
convert it to use maple trees instead, it is more modern.

Acked-by: David Rhodes <david.rhodes@cirrus.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230609-asoc-cirrus-maple-v1-3-b806c4cbd1d4@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-13 12:11:02 +01:00
Mark Brown
7a230512d3
ASoC: cs35l33: Use maple tree register cache
The cs35l33 can only support single register read and write operations
so does not benefit from block writes. This means it gets no benefit from
using the rbtree register cache over the maple tree register cache so
convert it to use maple trees instead, it is more modern.

Acked-by: David Rhodes <david.rhodes@cirrus.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230609-asoc-cirrus-maple-v1-2-b806c4cbd1d4@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-13 12:11:01 +01:00
Mark Brown
176bb179f1
ASoC: cs35l32: Use maple tree register cache
The cs35l32 can only support single register read and write operations
so does not benefit from block writes. This means it gets no benefit from
using the rbtree register cache over the maple tree register cache so
convert it to use maple trees instead, it is more modern.

Acked-by: David Rhodes <david.rhodes@cirrus.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230609-asoc-cirrus-maple-v1-1-b806c4cbd1d4@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-13 12:11:00 +01:00
Jon Hunter
f9fd804aa0
ASoC: tegra: Fix Master Volume Control
Commit 3ed2b549b39f ("ALSA: pcm: fix wait_time calculations") corrected
the PCM wait_time calculations and in doing so reduced the calculated
wait_time. This exposed an issue with the Tegra Master Volume Control
(MVC) device where the reduced wait_time caused the MVC to fail. For now
fix this by setting the default wait_time for Tegra to be 500ms.

Fixes: 3ed2b549b39f ("ALSA: pcm: fix wait_time calculations")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://lore.kernel.org/r/20230613093453.13927-1-jonathanh@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-13 12:10:56 +01:00
Oswald Buddenhagen
58cc6133cc ALSA: emu10k1: actually show some S/PDIF status in /proc for E-MU cards
The file is called spdif-in, but we abused it to show only sample rates
from various sources. Rectify it as far as possible (the FPGA doesn't
give us a lot of information).

Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>

Link: https://lore.kernel.org/r/20230612191325.1315854-10-oswald.buddenhagen@gmx.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2023-06-13 07:47:34 +02:00
Oswald Buddenhagen
3ac251420b ALSA: emu10k1: add support for 12 kHz capture on Audigy
Fixes a tentative FIXME. Because we can.

Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
Link: https://lore.kernel.org/r/20230612191325.1315854-9-oswald.buddenhagen@gmx.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2023-06-13 07:47:16 +02:00
Oswald Buddenhagen
ca533448a0 ALSA: emu10k1: fix timer for E-MU cards at 44.1 kHz word clock
The timer was presuming a fixed 48 kHz word clock, like the rest of the
code.

Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
Link: https://lore.kernel.org/r/20230612191325.1315854-8-oswald.buddenhagen@gmx.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2023-06-13 07:46:58 +02:00
Oswald Buddenhagen
6cc8445046 ALSA: timer: minimize open-coded access to hw.resolution
Some info-querying code still used hw.resolution directly instead of
calling snd_timer_hw_resolution(), thus missing a possible
hw.c_resolution callback. This patch rectifies that.

Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
Link: https://lore.kernel.org/r/20230612191325.1315854-7-oswald.buddenhagen@gmx.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2023-06-13 07:43:38 +02:00
Oswald Buddenhagen
e68235c8aa ALSA: emu10k1: fix synthesizer pitch for E-MU cards at 44.1 kHz
This is only a very partial fix - the frequency-dependent envelope & LFO
register values aren't adjusted.

But I'm not sure they were even correct at 48 kHz to start with, as most
of them are precalculated by common code which assumes an EMU8K-specific
44.1 kHz word clock, and it seems somewhat unlikely that the hardware's
register interpretation was adjusted to compensate for the different
word clock.

In any case I'm not going to spend time on fixing that, as this code is
unlikely to be actually used by anyone today.

Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
Link: https://lore.kernel.org/r/20230612191325.1315854-6-oswald.buddenhagen@gmx.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2023-06-13 07:42:08 +02:00
Oswald Buddenhagen
19b89d15fa ALSA: emu10k1: fix sample rates for E-MU cards at 44.1 kHz word clock
Now that we know the actual word clock, we can:
- Put the resulting rate into the hardware info
- At 44.1 kHz word clock shift the rate for the pitch calculations,
  which presume a 48 kHz word clock

Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
Link: https://lore.kernel.org/r/20230612191325.1315854-5-oswald.buddenhagen@gmx.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2023-06-13 07:41:43 +02:00
Oswald Buddenhagen
e73b597e63 ALSA: emu10k1: query rate of external clock sources on E-MU cards
The value isn't used yet; the subsequent commits will do that.

This ignores the existence of rates above 48 kHz, which is fine, as the
hardware will just switch to the fallback clock source when fed with a
rate which is incompatible with the base clock multiplier, which
currently is always x1.

The sample rate display in /proc spdif-in is adjusted to reflect our
understanding of the input rates.

This is tested only with an 0404b card without sync card, so there is a
lot of room for improvement.

Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>

Link: https://lore.kernel.org/r/20230612191325.1315854-4-oswald.buddenhagen@gmx.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2023-06-13 07:41:07 +02:00
Oswald Buddenhagen
60985241bf ALSA: emu10k1: make available E-MU clock sources card-specific
The actually available clock sources depend on the available audio input
ports and dedicated clock input ports.

This includes refactoring the code to be data-driven to remain
manageable.

Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
Link: https://lore.kernel.org/r/20230612191325.1315854-3-oswald.buddenhagen@gmx.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2023-06-13 07:40:51 +02:00
Oswald Buddenhagen
1359886227 ALSA: emu10k1: split off E-MU fallback clock from clock source
So far, we set the fallback as a side effect of setting the source. But
the fallback makes no sense at all when an internal clock is selected.
Defaulting to 48k for S/PDIF & ADAT makes sense, but as that is the
global default and we're not changing it automatically any more, it's
just fine to leave it entirely to the explicit setting.

This changes the name of the pre-existing control to something more
appropriate (regardless of the split), so users will need to adjust
their mixer settings.

Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
Link: https://lore.kernel.org/r/20230612191325.1315854-2-oswald.buddenhagen@gmx.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2023-06-13 07:39:50 +02:00
Takashi Iwai
508b662b69 Merge branch 'topic/midi20' into for-next
As the updated MIDI 2.0 spec has been published freshly, this is a
catch up to add the support for new specs, especially UMP v1.1
features, on Linux kernel.

The new UMP v1.1 introduced the concept of Function Blocks (FB), which
is a kind of superset of USB MIDI 2.0 Group Terminal Blocks (GTB).
The patch set adds the support for FB as the primary information
source while keeping the parse of GTB as fallback.  Also UMP v1.1
supports the groupless messages, the protocol switch, static FBs, and
other new fundamental features, and those are supported as well.

Link: https://www.midi.org/midi-articles/details-about-midi-2-0-midi-ci-profiles-and-property-exchange
Link: https://lore.kernel.org/r/20230612081054.17200-1-tiwai@suse.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2023-06-13 07:37:59 +02:00
Mark Brown
597d364cd7
ASoC: Intel: avs: remove redundant dapm routes
Merge series from Brent Lu <brent.lu@intel.com>:

This patch series remove redundant dapm routes declared in multiple machine
drivers. These routes will be created by snd_soc_dapm_connect_dai_link_widgets()
during soundcard initialization. Following is the kernel log from a KBL
chromebook nocturne.

dmic:
[   13.773455] avs_dmic avs_dmic: connected DAI link dmic-codec:Capture -> dmic-platform:DMIC Rx
[   13.773460] avs_dmic avs_dmic: connected DAI link dmic-codec:Capture -> dmic-platform:DMIC WoV Rx

max98373:
[   14.079536] avs_max98373 avs_max98373.1: connected DAI link avs_max98373.1-platform:ssp0 Tx -> i2c-MX98373:00:Right HiFi Playback
[   14.079545] avs_max98373 avs_max98373.1: connected DAI link i2c-MX98373:00:Right HiFi Capture -> avs_max98373.1-platform:ssp0 Rx
[   14.079550] avs_max98373 avs_max98373.1: connected DAI link avs_max98373.1-platform:ssp0 Tx -> i2c-MX98373:01:Left HiFi Playback
[   14.079554] avs_max98373 avs_max98373.1: connected DAI link i2c-MX98373:01:Left HiFi Capture -> avs_max98373.1-platform:ssp0 Rx

hdaudio:
[   14.094818] avs_hdaudio avs_hdaudio.2: connected DAI link hdaudioB0D2-platform:hdaudioB0D2-cpu0 Tx -> hdaudioB0D2:HDMI 0 Playback
[   14.094824] avs_hdaudio avs_hdaudio.2: connected DAI link hdaudioB0D2-platform:hdaudioB0D2-cpu1 Tx -> hdaudioB0D2:HDMI 1 Playback
[   14.094828] avs_hdaudio avs_hdaudio.2: connected DAI link hdaudioB0D2-platform:hdaudioB0D2-cpu2 Tx -> hdaudioB0D2:HDMI 2 Playback
2023-06-12 18:35:11 +01:00
Mark Brown
487db53bb5
ASoC: mediatek: mt8173: Fix error paths
Merge series from Ricardo Ribalda Delgado <ribalda@chromium.org>:

ASoC: mediatek: mt8173, presented a couple of error paths errors, lets
fix them.
2023-06-12 18:26:12 +01:00
Takashi Iwai
01dfa8e969 ALSA: ump: Add info flag bit for static blocks
UMP v1.1 spec allows to inform whether the function blocks are static
and not dynamically updated.  Add a new flag bit to
snd_ump_endpoint_info to reflect that attribute, too.

The flag is set when a USB MIDI device is still in the old MIDI 2.0
without UMP 1.1 support.  Then the driver falls back to GTBs, and they
are supposed to be static-only.

Link: https://lore.kernel.org/r/20230612081054.17200-10-tiwai@suse.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2023-06-12 18:22:34 +02:00
Takashi Iwai
6a8b4800ae ALSA: seq: ump: Notify UMP protocol change to sequencer
UMP v1.1 supports the protocol switch via a UMP Stream message.  When
it's received, we need to take care of the midi_version field in the
corresponding sequencer client, too.

This patch introduces a new ops to notify the protocol change to
snd_seq_ump_ops for handling it.

Link: https://lore.kernel.org/r/20230612081054.17200-9-tiwai@suse.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2023-06-12 18:22:33 +02:00
Takashi Iwai
174a6dfbc1 ALSA: seq: ump: Notify port changes to system port
For allowing applications to track the FB active changes, this patch
adds the notification from the system port at each time a FB change is
handled and the active flag or re-grouping happens.

Link: https://lore.kernel.org/r/20230612081054.17200-8-tiwai@suse.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2023-06-12 18:22:32 +02:00
Takashi Iwai
4a16a3af05 ALSA: seq: ump: Handle FB info update
This patch implements the handling of the dynamic update of FB info.

When the FB info update is received after the initial parsing, it
means the dynamic FB info update.  We compare the result, and if the
actual update is detected, it's notified via a new ops,
notify_fb_change, to the sequencer client, and the corresponding
sequencer ports are updated accordingly.

Link: https://lore.kernel.org/r/20230612081054.17200-7-tiwai@suse.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2023-06-12 18:22:31 +02:00
Takashi Iwai
5437ac9bad ALSA: seq: ump: Handle groupless messages
The UMP Utility and Stream messages are "groupless", i.e. an incoming
groupless packet should be sent only to the UMP EP port, and the event
with the groupless message is sent to UMP EP as is without the group
translation per port.

Also, the former reserved bit 0 for the client group filter is now
used for groupless events.  When the bit 0 is set, the groupless
events are filtered out and skipped.

Link: https://lore.kernel.org/r/20230612081054.17200-6-tiwai@suse.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2023-06-12 18:22:29 +02:00