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4 Commits

Author SHA1 Message Date
Michal Simek
598acab44d microblaze: Define correct L1_CACHE_SHIFT value 
Microblaze cacheline length is configurable and current cpu
uses two cacheline length 4 and 8.

We are taking conservative maximum value to be sure that cacheline
alignment is satisfied for all cases.

Here is the calculation for cacheline lenght 8  32bit=4Byte values
which is corresponding with SHIFT 5.

Signed-off-by: Michal Simek <monstr@monstr.eu>
 2010-05-06 11:21:59 +02:00
Michal Simek
a1f55113ca microblaze: Move cache macro from cache.h to cacheflush.h 
Signed-off-by: Michal Simek <monstr@monstr.eu>
 2009-12-14 08:45:00 +01:00
Michal Simek
ceb8944b3a microblaze: Remove uncache shadow condition 
Uncached shadow feature is not supported in current
kernel code that's why I removed it.

Signed-off-by: Michal Simek <monstr@monstr.eu>
 2009-04-23 16:09:16 +02:00
Michal Simek
8beb8503bf microblaze_v8: cache support 
Reviewed-by: Ingo Molnar <mingo@elte.hu>
Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com>
Acked-by: John Linn <john.linn@xilinx.com>
Acked-by: John Williams <john.williams@petalogix.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
 2009-03-27 14:25:16 +01:00