42022 Commits

Author SHA1 Message Date
Tony Lindgren
aced048432 Merge branch 'for-4.3/ti-clk-dt' of https://github.com/t-kristo/linux-pm into omap-for-v4.3/dt-v2 2015-08-12 01:38:08 -07:00
Maxime Ripard
06f282757a ARM: sun9i: Wrap the clock-indices
Wrap the clock-indices to match the wrapping of the clock-output-names in
order to make it easier to match indices to names.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-08-12 00:59:13 -07:00
Maxime Ripard
c0a6e360a4 ARM: sun8i: Add clock indices
The A23 and A33 gates have a non continuous set of clock IDs that are
valid. Add the clock-indices property to the DT to express this.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-08-12 00:59:11 -07:00
Maxime Ripard
6bfe30b2fd ARM: sun7i: Add clock indices
The A20 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-08-12 00:59:09 -07:00
Maxime Ripard
dbbb69223c ARM: sun6i: Add clock indices
The A31 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-08-12 00:59:07 -07:00
Maxime Ripard
dd4de433aa ARM: sun5i: Add clock indices
The A10s and A13 gates have a non continuous set of clock IDs that are
valid. Add the clock-indices property to the DT to express this.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-08-12 00:59:04 -07:00
Maxime Ripard
a38540068f ARM: sun4i: Add clock indices
The A10 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-08-12 00:59:02 -07:00
Geert Uytterhoeven
60c0745a80 ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-08-12 11:15:28 +09:00
Geert Uytterhoeven
4b31bad51f ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-08-12 11:15:27 +09:00
Geert Uytterhoeven
797a0626e0 ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.  Notable
exceptions are the "display" and "sound" nodes, which represent multiple
SoC devices, each having their own MSTP clocks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-08-12 11:15:27 +09:00
Geert Uytterhoeven
484adb0058 ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.  Notable
exceptions are the "display" and "sound" nodes, which represent multiple
SoC devices, each having their own MSTP clocks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-08-12 11:15:27 +09:00
Geert Uytterhoeven
33c3632a3f ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-08-12 11:15:26 +09:00
Geert Uytterhoeven
a670f3667a ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.  A notable
exception is the "sound" node, which represents multiple SoC devices,
each having their own MSTP clocks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-08-12 11:15:26 +09:00
Geert Uytterhoeven
cbe1f83818 ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-08-12 11:15:26 +09:00
Simon Horman
3f3f0ea0af Merge branch 'clk-for-v4.3' into dt-for-v4.3 2015-08-12 11:15:19 +09:00
Geert Uytterhoeven
f04b486d34 clk: shmobile: rz: Add CPG/MSTP Clock Domain support
Add Clock Domain support to the RZ Clock Pulse Generator (CPG) driver
using the generic PM Domain.  This allows to power-manage the module
clocks of SoC devices that are part of the CPG/MSTP Clock Domain using
Runtime PM, or for system suspend/resume.

SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-08-12 10:31:28 +09:00
Geert Uytterhoeven
8bc964aa25 clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
Add Clock Domain support to the R-Car M1A Clock Pulse Generator (CPG)
driver using the generic PM Domain.  This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.

SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-08-12 10:31:27 +09:00
Krzysztof Kozlowski
2b347c6494 ARM: exynos_defconfig: Enable cpufreq-dt driver
With the latest patches the cpufreq-dt can be used on multiple
Exynos SoCs: 3250, 4210, 4212, 4412 and 5250.

Enable it along with default ondemand governor to conserve the energy,
reduce temperature while maintaining acceptable performance.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
2015-08-12 08:17:31 +09:00
Javier Martinez Canillas
c3e71f4b5f ARM: multi_v7_defconfig: Enable max77802 regulator
The Exynos5420 based Peach Pit and Exynos5800 based Peach Pi Chromebooks
use the Maxim max77802 Power Management IC (PMIC). This PMIC has besides
other devices, a set of regulators that can be controller over I2C.

Commit f3caa529c6f5 ("ARM: multi_v7_defconfig: Enable max77802 regulator,
rtc and clock drivers") was supposed to enable the config option for the
regulator driver as a module but the final version that landed did not
include this. The commit was modified and the REGULATOR_MAX77802 removed
since it was thought to be useless.

Unfortunately that's not the case for the mentioned reason above so this
patch enables the needed Kconfig option.

Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
[kgene@kernel.org: fixed ordering according to make savedefconfig]
Signed-off-by: Kukjin Kim <kgene@kernel.org>
2015-08-12 08:15:02 +09:00
Kishon Vijay Abraham I
73c8f0cbb0 ARM: dts: am57xx-evm: Add 'gpios' property with gpio2_8
gpio2_8 is connected to the PCIe_RESETn line and it has to be driven low to
reset the PCIe cards.  Add gpios property to PCIe DT node.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Tony Lindgren <tony@atomide.com>
2015-08-11 15:59:16 -05:00
Russell King
efaa6e266b firmware: qcom_scm-32: replace open-coded call to __cpuc_flush_dcache_area()
Rathe rthan directly accessing architecture internal functions, provide
an "method"-centric wrapper for qcom_scm-32 to do what's necessary to
ensure that the secure monitor can see the data.  This is called
"secure_flush_area" and ensures that the specified memory area is
coherent across the secure boundary.

Acked-by: Andy Gross <agross@codeaurora.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-08-11 18:45:00 +01:00
Eric Anholt
b35ef52672 ARM: bcm2835: Add the firmware driver information to the RPi DT
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2015-08-11 16:56:32 +01:00
Anson Huang
3603257553 ARM: dts: imx6ul: add snvs power key support
Add i.MX6UL SNVS power key support.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:27 +08:00
Anson Huang
5b032872c9 ARM: dts: imx6ul: add RTC support
Add RTC support for i.MX6UL.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:27 +08:00
Anson Huang
18619ff55d ARM: dts: imx6ul: enable GPC as extended interrupt controller
Enable GPC as extended interrupt controller of
GIC, as GPC needs to manage wakeup source for
low power modes.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:26 +08:00
Anson Huang
461aa6d723 ARM: dts: imx6sx: correct property name for wakeup source
Commit(def56bb input: snvs_pwrkey: use "wakeup-source"
as deivce tree property name) replaces the property name
of "wakeup" with "wakeup-source", update this change
in i.MX6SX dtsi accordingly.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:26 +08:00
Stefan Agner
def0641e2f ARM: dts: add property for maximum ADC clock frequencies
The ADC clock frequency is limited depending on modes used. Add
device tree property which allow to set the mode used and the
maximum frequency ratings for the instance. These allows to
set the ADC clock to a frequency which is within specification
according to the actual mode used.

Acked-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:25 +08:00
Frank Li
abb9f253cd ARM: dts: imx7d: enable snvs rtc, onoffkey and power off
Change SNVS rtc to syscon interface.
Enable onoff key and power off function.

Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:25 +08:00
Fugang Duan
5e8cdb0139 ARM: dts: imx6ul-14x14-evk: add fec1 and fec2 support
Add ethernet fec1 and fec2 support for i.MX6ul 14x14 evk board.

Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:24 +08:00
Fugang Duan
01f3dc7de3 ARM: dts: imx: add fec1 and fec2 nodes for SOC i.MX6UL
SOC i.MX6UL has two ethernet MACs, add fec1 and fec2 support for i.MX6UL.

Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:24 +08:00
Philippe Reynes
91eca8d57c ARM: dts: imx27: add support of internal rtc
Add support of internal rtc on imx27.

Signed-off-by: Philippe Reynes <tremyfr@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:23 +08:00
Stefan Agner
4f182ff7d4 ARM: dts: vf-colibri: define stdout-path property
Define Vybrid's UART0, connected to the Colibri pinout UART_A, as
standard output.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:22 +08:00
Claudiu Manoil
055223d4d2 ARM: dts: ls1021a: Enable the eTSEC ports on QDS and TWR
This enables the available eTSEC ethernet ports for the
ls1021aqds and ls1021atwr boards.
For the QDS, SGMII connections (via riser cards) are assumed
for the eTSEC0 and eTSEC1 ports as default configuration.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:22 +08:00
Claudiu Manoil
d69cb5d7ea ARM: dts: ls1021a: Add the eTSEC controller nodes
Add basic support for all the eTSEC controllers on the
ls1021a SoC.  Second interrupt group register blocks
and their corresponding Rx/Tx/Err interrupt sources are
included as well for each eTSEC node.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:21 +08:00
Frank Li
5ff807a567 ARM: dts: imx6ul: add qspi support
enable qspi support

Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:21 +08:00
Frank Li
4e06dfabe8 ARM: dts: imx6ul: fix low case define in imx6ul-pinfunc.h
some pin name should be capital "_B" instead of "_b"

Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:20 +08:00
Frank Li
cad2cb69f5 ARM: dts: imx6ul: add usb host and function support
Enable usb host and function driver

Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:20 +08:00
Sanchayan Maity
9b1793afef ARM: dts: vfxxx: Add io-channel-cells property for ADC node
This commit adds io-channel-cells property to the ADC node. This
property is required in order for an IIO consumer driver to work.
Especially required for Colibri VF50, as the touchscreen driver
uses ADC channels with the ADC driver based on IIO framework.

Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:19 +08:00
Alison Wang
50897cb6fa ARM: dts: ls1021a: Add dts nodes for audio on LS1021A
This patch adds dts nodes for audio on LS1021A.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:19 +08:00
Peter Chen
0f92fd49ff ARM: imx6qdl-sabreauto.dtsi: enable USB support
Add USBOTG and USB host 1 support

Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:18 +08:00
Frank Li
95d739b5ca ARM: dts: imx: update snvs to use syscon access register
snvs is MFP device. Change dts to use syscon to allocate register resource.
snvs power off also switch to common syscon-poweroff

Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:17 +08:00
Frank Li
a5fcccbc6e ARM: dts: imx: add imx6ul and imx6ul evk board support
Add new SOC i.MX6UL dtb file support, including evk board
support

i.MX6 Ultralite processor include one ARM cortext-A7 core.
Offer high perfomance and lowest power consumption.

Main included:
- 4 MMC/SD/SDIO
- 2 USB 2.0 OTG
- 3 I2S/SAI/AC97
- 4 eCSPI
- 4 I2C
- 2 ENET
- 2 CAN
- 3 wdog
- ASRC
- 8 uart
- LCDIF
- PXP

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Fancy Fang <chen.fang@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:17 +08:00
Frank Li
7eeb662ad2 ARM: dts: add i.mx6ul pin function include file
add pin mux define file

Signed-off-by: Bai Ping <b51503@freescale.com>
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:16 +08:00
Cory Tusar
3b7816bade ARM: dts: vfxxx: Include support for esdhc0 functionality.
Extend the existing Vybrid eSDHC devicetree implementation to also
describe the esdhc0 functional block.

Tested on a custom VF610-based board with a Toshiba THGBM1G5D2EBAI7 eMMC
module attached to esdhc0.

Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:15 +08:00
Fabio Estevam
ed339363de ARM: dts: imx6qdl-sabreauto: Allow HDMI and LVDS to work simultaneously
Currently it is not possible to have HDMI and LVDS working simultaneously,
because both ports try to use PLL5.

Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be
driven from independent sources.

With this change the LDB pixel clock goes to 68.57 MHz, which is still
within the valid range for the HSD100PXN1 LVDS panel.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:15 +08:00
Cory Tusar
6f5e69672e ARM: dts: vfxxx: Include support for qspi1 functionality.
This commit extends the existing Vybrid QSPI devicetree implementation
to also describe the qspi1 functional block.

Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:14 +08:00
Cory Tusar
f4b89232f2 ARM: dts: vf610: Add missing QuadSPI register mapping and names.
Both 'reg' and 'reg-names' are required properties according to binding
documentation, and both should contain two items.

Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:14 +08:00
Haikun Wang
c47d6e380b ARM: dts: ls1021a: Update 'dspi' device node compatible string
Freescale DSPI driver has been updated and supports TCF interrupt type now.
In the new driver we choose the interrupt type according the compatible
string of the device node.
This patch update the compatible string of DSPI device node of LS1021A in
order to use the correct interrupt type.

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:13 +08:00
Frank Li
3adab7c796 ARM: dts: imx7d: add cortex-a7 coresight component
Added etm, etb, funnel and replicator

usage example:

    echo 1 >/sys/bus/coresight/devices/30086000.etr/enable_sink
    echo 1 >/sys/bus/coresight/devices/3007c000.etm/enable_source

        coresight-tmc 30086000.etr: TMC enabled
        coresight-replicator replicator.1: REPLICATOR enabled
        coresight-tmc 30084000.tmc: TMC enabled
        coresight-funnel 30083000.funnel: FUNNEL inport 0 enabled
        coresight-funnel 30041000.funnel: FUNNEL inport 0 enabled
        coresight-etm3x 3007c000.etm: ETM tracing enabled

    etm enable here.
    trace data save at /dev/30086000.etr

    cat /dev/30086000.etr > trace.data

        coresight-tmc 30086000.etr: TMC read start
        coresight-tmc 30086000.etr: TMC read end

    use ptm2human(https://github.com/hwangcc23/ptm2human) to show trace data

    ptm2human -i trace.data

Signed-off-by: Frank Li <Frank.Li@freescale.com>
Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:12 +08:00
Fabio Estevam
7804fbcfe5 ARM: dts: imx6qdl-nitrogen6x: Allow HDMI and LVDS to work simultaneously
Currently it is not possible to have HDMI and LVDS working simultaneously,
because both ports try to use PLL5.

Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be
driven from independent sources.

With this change the LDB pixel clock goes to 68.57 MHz, which is still
within the valid range for the HSD100PXN1 LVDS panel.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Gary Bisson <gary.bisson@boundarydevices.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-08-11 23:15:12 +08:00