1878 Commits

Author SHA1 Message Date
Dennis YC Hsieh
5f6e560c2d soc: mediatek: cmdq: add write_s function
add write_s function in cmdq helper functions which
writes value contains in internal register to address
with large dma access support.

Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>
Link: https://lore.kernel.org/r/1594136714-11650-3-git-send-email-dennis-yc.hsieh@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-25 17:27:31 +02:00
Dennis YC Hsieh
2b8cf38343 soc: mediatek: cmdq: add address shift in jump
Add address shift when compose jump instruction
to compatible with 35bit format.

Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>
Reviewed-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Link: https://lore.kernel.org/r/1594136714-11650-2-git-send-email-dennis-yc.hsieh@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-25 17:27:26 +02:00
Krzysztof Kozlowski
11b490c6ae soc: mediatek: mtk-infracfg: Fix kerneldoc
Fix W=1 compile warnings (invalid kerneldoc):

    drivers/soc/mediatek/mtk-infracfg.c:34: warning: Function parameter or member 'infracfg' not described in 'mtk_infracfg_set_bus_protection'
    drivers/soc/mediatek/mtk-infracfg.c:34: warning: Excess function parameter 'regmap' description in 'mtk_infracfg_set_bus_protection'

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200729074415.28393-1-krzk@kernel.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-25 17:27:24 +02:00
Kevin Hilman
5aabf1180f soc: amlogic: pm-domains: use always-on flag
Rather than use a governor to keep these domains always-on, instead
use the flag GENPD_FLAG_ALWAYS_ON.  This has the same effect, but with
much lower overhead since the governor path is not used at all.

Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200921222135.7145-1-khilman@baylibre.com
2020-09-24 09:50:01 -07:00
Wang Hai
d97b957e32 soc: fsl: qe: Remove unnessesary check in ucc_set_tdm_rxtx_clk
Fix smatch warning:

drivers/soc/fsl/qe/ucc.c:526
 ucc_set_tdm_rxtx_clk() warn: unsigned 'tdm_num' is never less than zero.

'tdm_num' is u32 type, never less than zero.

Signed-off-by: Wang Hai <wanghai38@huawei.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
2020-09-22 18:25:29 -05:00
Liu Shixin
5ed2da99e3 soc: fsl: qman: convert to use be32_add_cpu()
Signed-off-by: Liu Shixin <liushixin2@huawei.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
2020-09-22 18:16:15 -05:00
Jason Yan
72f7fe2d6a soc: fsl: dpio: remove set but not used 'addr_cena'
This addresses the following gcc warning with "make W=1":

drivers/soc/fsl/dpio/qbman-portal.c: In function
‘qbman_swp_enqueue_multiple_direct’:
drivers/soc/fsl/dpio/qbman-portal.c:650:11: warning: variable
‘addr_cena’ set but not used [-Wunused-but-set-variable]
  650 |  uint64_t addr_cena;
      |           ^~~~~~~~~

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Jason Yan <yanaijie@huawei.com>
Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
2020-09-22 17:43:54 -05:00
Krzysztof Kozlowski
750cf40c0f soc: fsl: qbman: Fix return value on success
On error the function was meant to return -ERRNO.  This also fixes
compile warning:

  drivers/soc/fsl/qbman/bman.c:640:6: warning: variable 'err' set but not used [-Wunused-but-set-variable]

Fixes: 0505d00c8dba ("soc/fsl/qbman: Cleanup buffer pools if BMan was initialized prior to bootup")
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
2020-09-22 17:42:22 -05:00
Krzysztof Kozlowski
bc38325703 soc: actions: include header to fix missing prototype
Include the header with prototype of owl_sps_set_pg to fix:

  drivers/soc/actions/owl-sps-helper.c:16:5: warning: no previous prototype for 'owl_sps_set_pg' [-Wmissing-prototypes]

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2020-09-22 12:45:16 +05:30
Qinglang Miao
74e0e43a09 soc: ti: Convert to DEFINE_SHOW_ATTRIBUTE
Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code.

Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-09-20 19:30:30 -07:00
Neil Armstrong
525054782a soc: amlogic: meson-ee-pwrc: add support for the Meson AXG SoCs
The Power Controller in the Amlogic AXG SoCs is similar to the GXL one
but with less VPU memory domains to enable and a supplementary Audio
memory power domain.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20200917064702.1459-3-narmstrong@baylibre.com
2020-09-18 13:22:14 -07:00
Thierry Reding
639448912b arm64: tegra: Initial Tegra234 VDK support
The NVIDIA Tegra234 VDK is a simulation platform for the Orin SoC. It
supports a subset of the peripherals that will be available in the final
chip and serves as a bootstrapping platform.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-18 15:58:07 +02:00
Thierry Reding
34e214a996 soc/tegra: pmc: Add Tegra234 support
The PMC block is largely similar to that found on earlier chips, but
not completely compatible. Allow binding to the instantiation found on
Tegra234.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-18 15:55:37 +02:00
Thierry Reding
f98485e4ed soc/tegra: pmc: Reorder reset sources/levels definitions
Move the definitions of reset sources and levels into a more natural
location.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-18 15:55:33 +02:00
Thierry Reding
03d2852307 soc/tegra: misc: Add Tegra234 support
The MISC block is largely similar to that found on earlier chips, but
not completely compatible. Allow binding to the instantiation found on
Tegra234.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-18 15:55:31 +02:00
Thierry Reding
1f44febf71 soc/tegra: fuse: Add Tegra234 support
Add support for FUSE block found on the Tegra234 SoC, which is largely
similar to the IP found on previous generations.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-18 15:55:29 +02:00
Thierry Reding
52e6d399a4 soc/tegra: fuse: Implement tegra_is_silicon()
This function can be used by drivers to determine whether code is
running on silicon or on a simulation platform.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-18 15:55:26 +02:00
Thierry Reding
775edf7856 soc/tegra: fuse: Extract tegra_get_platform()
This function extracts the PRE_SI_PLATFORM field from the HIDREV
register and can be used to determine which platform the kernel runs on
(silicon, simulation, ...). Note that while only Tegra194 and later
define this field, it should be safe to call this on prior generations
as well since this field should read as 0, indicating silicon.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-18 15:55:22 +02:00
Qilong Zhang
2899347249 soc: qcom: llcc: use devm_platform_ioremap_resource_byname()
Use the devm_platform_ioremap_resource_byname() helper instead of
calling platform_get_resource_byname() and devm_ioremap_resource()
separately.

Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com>
Link: https://lore.kernel.org/r/20200916111517.99670-1-zhangqilong3@huawei.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-17 04:24:49 +00:00
Yoshihiro Shimoda
1b4298f000 soc: renesas: r8a779a0-sysc: Add r8a779a0 support
Add support for R-Car V3U (R8A779A0) SoC power areas and register
access, because register specification differs from R-Car Gen2/3.

Inspired by patches in the BSP by Tho Vu.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1599810232-29035-5-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-16 08:57:31 +02:00
Sibi Sankar
ba34f977c3 soc: qcom: apr: Fixup the error displayed on lookup failure
APR client incorrectly prints out "ret" variable on pdr_add_lookup failure,
it should be printing the error value returned by the lookup instead.

Fixes: 8347356626028 ("soc: qcom: apr: Add avs/audio tracking functionality")
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20200915154232.27523-1-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-15 16:12:59 +00:00
Sibi Sankar
7a366707bb soc: qcom: pdr: Fixup array type of get_domain_list_resp message
The array type of get_domain_list_resp is incorrectly marked as NO_ARRAY.
Due to which the following error was observed when using pdr helpers with
the downstream proprietary pd-mapper. Fix this up by marking it as
VAR_LEN_ARRAY instead.

Err logs:
qmi_decode_struct_elem: Fault in decoding: dl(2), db(27), tl(160), i(1), el(1)
failed to decode incoming message
PDR: tms/servreg get domain list txn wait failed: -14
PDR: service lookup for tms/servreg failed: -14

Tested-by: Rishabh Bhatnagar <rishabhb@codeaurora.org>
Fixes: fbe639b44a82 ("soc: qcom: Introduce Protection Domain Restart helpers")
Reported-by: Rishabh Bhatnagar <rishabhb@codeaurora.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20200914145807.1224-1-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-14 23:53:29 +00:00
Konrad Dybcio
a32a43e00e soc: qcom: socinfo: Add msm8992/4 and apq8094 SoC IDs
Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Link: https://lore.kernel.org/r/20200602201229.322578-1-konradybcio@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-14 23:27:24 +00:00
Olof Johansson
bd2fad8cd3 This pull request contains Broadcom SoCs drivers changes for 5.10,
please pull the following:
 
 - Alvaro adds support for the BCM63xx (DSL) SoCs power domain controller
   and adds support for the 6318, 6328, 6362, 63268.
 
 - Florian adds support for tuning the Bus Interface Unit on 72164 and
   72165, enables the Brahma-B53 and Cortex-A72 read-ahead cache for the
   64-bit capable ARCH_BRCMSTB platforms, and finally updates the GISB
   driver to support breakpoint notifications.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAl9ZkK4ACgkQh9CWnEQH
 BwS8bQ//dn66KKeK2Fcw6pofTypsE7y69P2Jz7vA8IkYigNaNwIWABXXE+/FXrPE
 ZVk9se/ZAI/kvWQXKj5T2JyjXWU8jphidwX0aK1xUymab60W6EdZUJcTiKdsdamA
 KGSAQ0jjWaNuZHnNR2nsqa4OLDrnQz2ujdWCnz9SSBNtPFcAknbj+nkicbpWmHb7
 1fjBXg7e+RkUuaHGNETIkKnjdEA/e2frlTCzwendsLTgJkhbr9j9y6jAOtJiXjE4
 +UQd84cEPsuvSrx6dx6pnCVoL19m2aPFE9JTDVCXVYCOinjm+gQDXQTl8w+HvoZn
 /w0deVOJSOF+YHoRbC7xLghaY2jjRmM86jjmopSB7/OF5KUbkuMj1Nz5xQxUI7gA
 BuvRQvry+TedEiY1vfsDnrJZpv3vZTS2BRkTfiZXvhtfDM/unMr9L6vScxzQU7gA
 Gj2hPEai3bB+pfTB+e1H4IAWFmQXgS+3Q+JpCtgHjZFZtmYy89MaJK5TY88pYceR
 ZfnK6aHhHXNF3L594CYCNxZBovC2Jt/Mp6+MIPgFpvwTFKhqoLIjUP5bnuZRqHZ6
 yVz0WJgU6R7FPtp8uTwES5moreeAWMdVdzHdZvTkOrPzRvBpT1tMWpk00eFaAn7E
 PlTdM5OMuxDi2tZKcLNCW92To1Un0YRnMLZh8Q5sSS9MekY++hk=
 =njcZ
 -----END PGP SIGNATURE-----

Merge tag 'arm-soc/for-5.10/drivers' of https://github.com/Broadcom/stblinux into arm/drivers

This pull request contains Broadcom SoCs drivers changes for 5.10,
please pull the following:

- Alvaro adds support for the BCM63xx (DSL) SoCs power domain controller
  and adds support for the 6318, 6328, 6362, 63268.

- Florian adds support for tuning the Bus Interface Unit on 72164 and
  72165, enables the Brahma-B53 and Cortex-A72 read-ahead cache for the
  64-bit capable ARCH_BRCMSTB platforms, and finally updates the GISB
  driver to support breakpoint notifications.

* tag 'arm-soc/for-5.10/drivers' of https://github.com/Broadcom/stblinux:
  bus: brcmstb_gisb: Add support for breakpoint interrupts
  dt-bindings: bus: Document breakpoint interrupt for gisb-arb
  soc: bcm: brcmstb: biuctrl: Change RAC data line prefetching after 4 consecutive lines
  soc: bcm: brcmstb: biuctrl: Change RAC prefetch distance from +/-1 to +/- 2
  soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72165
  soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72164
  MIPS: BMIPS: dts: add BCM63268 power domain support
  MIPS: BMIPS: dts: add BCM6362 power domain support
  MIPS: BMIPS: dts: add BCM6328 power domain support
  soc: bcm: add BCM63xx power domain driver
  MIPS: BMIPS: add BCM6318 power domain definitions
  MIPS: BMIPS: add BCM63268 power domain definitions
  MIPS: BMIPS: add BCM6362 power domain definitions
  MIPS: BMIPS: add BCM6328 power domain definitions
  dt-bindings: soc: brcm: add BCM63xx power domain binding
  soc: bcm: brcmstb: biuctrl: Enable Read-ahead cache
  bus: brcmstb_gisb: Shorten prints

Link: https://lore.kernel.org/r/20200912032153.1216354-3-f.fainelli@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2020-09-13 11:40:18 -07:00
Olof Johansson
989286ffe8 Add initial genpd support for omaps to drop more platform data
We now drop legacy platform data for RTC on am3, am4 and dra7.
 And we add initial genpd support for PRM (Power and Reset Manager)
 and use it to drop legacy platform data for am3 sgx and omap4/5
 l4_abe interconnect instance.
 -----BEGIN PGP SIGNATURE-----
 
 iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAl9Qsw8RHHRvbnlAYXRv
 bWlkZS5jb20ACgkQG9Q+yVyrpXNnORAAwV+49gsZdnGLQxqzLThegu5auzfQuRdZ
 E82KGonAjoHONaBdk+pgVrEePpcJTUbUNQm8HeQRjusp/5CR8C+S6A9/RD+R1crc
 F+9gDsbTuBSkUkOAVkMT6oGPom8zN8bISJ4gFymLoGsT7MTD3K1nK6wVXpRhCJs6
 R2z/KpFIPMfz0psuYEgl5Uwu9RA+yi7P8ePulEBoOfOfMU/70nTRNhFoAAQK2vyO
 fvQCRY+4gf6Y76iY+WBXlf/2Iq4Kd4Rbs/Jr3MBC9ov8owqZKlnZ4u3HXrCQPin5
 ULS256Een4g8lnVZr48Dc0v6PWvu3AoHH6+gGsxFozKvmh+x5UXW+gUYozsvd/cW
 y61RARwo0F1ZJRil95Qgp/0jk0uAjTPdU5q5/owMIaFEoHK+1oHruj7dajdoJ22y
 9URXuCMwMKJIcefGvu8BWwuCZQx0zF16NffYmqkm3DPIobzNzCcMIbKNq6LPpgD4
 AnDtaw9Bhoq3O4/pVI3AMqEpBtHRJdWBoObFG3Lg3TpYDIrWSPzjaDo+HNwgD5u4
 7a1AqVrl1ZkTZIuJSfS7zZdeL5l8K02qYM1yjX13PderGTCzGmFVR4qRmItT9oVS
 zIl0mnoFngUxw9qiTRHgkcQ90Z65KwWcJDBoX5bVxanEnOQXdToaJ3TG5Fh1L4lv
 MWJhSe46Pdw=
 =w5Zl
 -----END PGP SIGNATURE-----

Merge tag 'omap-for-v5.10/ti-sysc-drop-pdata-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/soc

Add initial genpd support for omaps to drop more platform data

We now drop legacy platform data for RTC on am3, am4 and dra7.
And we add initial genpd support for PRM (Power and Reset Manager)
and use it to drop legacy platform data for am3 sgx and omap4/5
l4_abe interconnect instance.

* tag 'omap-for-v5.10/ti-sysc-drop-pdata-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: Drop legacy platform data for dra7 rtcss
  ARM: OMAP2+: Drop legacy platform data for am3 and am4 rtc
  soc: ti: pm33xx: Simplify RTC usage to prepare to drop platform data
  ARM: dts: Configure omap4 and 5 l4_abe for genpd and drop platform data
  ARM: dts: Configure am3 and am4 sgx for genpd and drop platform data
  soc: ti: omap-prm: Configure omap4 and 5 l4_abe power domain
  soc: ti: omap-prm: Configure sgx power domain for am3 and am4
  soc: ti: omap-prm: Add basic power domain support
  dt-bindings: omap: Update PRM binding for genpd

Link: https://lore.kernel.org/r/pull-1599132307-761202@atomide.com-2
Signed-off-by: Olof Johansson <olof@lixom.net>
2020-09-13 11:17:42 -07:00
Olof Johansson
c9c7ddd0d7 Versatile SoC updates for the v5.10 kernel cycle:
- Drop a static qualifier in integrator_soc_init()
 - Remove Integrator and Versatile from PHYS_OFFSET
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAl9OEHkACgkQQRCzN7AZ
 XXPFcQ/+JV/W2nI5QQ0tE0OpUwDdfmkU93dEgF38tNB97LnG/mhS5T7u78u8/d8H
 CBurShFXq3I/75Gfxno741K1h3qtf0XlYsuQ9vN0aDP3lqcgaQtfAlYDA/cg7z6a
 ppanIC/Akxu6zEETPCbG+j0n/TIQqWuT+0y+65jbeKm+eAEVDy/sPIXuVd5YTDd2
 8f1EjLywMzSDfmn3YP6AOzoQWg0HPC52bzea0MAFv0L9vOa2X4/SkJnFGPyJu46h
 jgrobaaqOKNq/7lxUfXBsfEEE5QbEQ26G67rIVAjYGk8CjdfWg0qJUBsDpKgnfVt
 79VnKqk13YJ2ywlD2+IG+rbWraE+ZI9aShITx3JFR3JM9Nsjbae/myYN+9Hqh75v
 Sxs7V0mEqtt4sf0+Dxvw97FmOGIB827V1q4kzglk9jiP1flf+orVhFYjtbNzEQld
 RTceCK9W4thPkJJnCx6id0GkYG0EnIaCrfY3pMuZDvO45M15E9zdPD+0FzwtYtFE
 jcGtINCfKOUJujLu3QfwbheInHTY+MnEo6crI0q7MRElg8YDtSWiSjyBJ2A/Fcs1
 iGIrrthBNoBfNBCODBuYE8WbjTpZ8SX8OQLdjcFqjmzrTlgdcIJQZVqNGn2fGaEi
 t5Ga2+gU3YFcqm9XsK7tWNMbwi+IvxzkjWRdPDplNoYClcK/i5w=
 =xtzo
 -----END PGP SIGNATURE-----

Merge tag 'versatile-soc-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into arm/soc

Versatile SoC updates for the v5.10 kernel cycle:

- Drop a static qualifier in integrator_soc_init()
- Remove Integrator and Versatile from PHYS_OFFSET

* tag 'versatile-soc-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
  ARM: versatile: Remove Integrator and Realview from PHYS_OFFSET
  soc: integrator: Drop pointless static qualifier in integrator_soc_init()

Link: https://lore.kernel.org/r/CACRpkdYYDSg8FAjJAqew5yEu7H1Y3E1rPN9TL25K31T=QWATuA@mail.gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2020-09-13 11:16:09 -07:00
Olof Johansson
465c335bb5 Samsung S3C24xx and S3C64xx machine code cleanup for v5.10
Big cleanup for the Samsung S3C24xx and S3C64xx platforms, although it
 also touches files shared with S5Pv210 and Exynos.  This is mostly Arnd
 Bergmann work which Krzysztof Kozlowski took over, rebased and polished.
 
 The goal is to cleanup, merge and finally make the Samsung S3C24xx and
 S3C64xx architectures multiplatform.  The multiplatform did not happen
 yet here - just cleaning up and merging into one arch/arm/mach-s3c
 directory.  However this is step forward for multiplatform or at least
 to keep this code still maintainable.
 
 This pulls also branch with changes for Samsung SoC sound drivers from
 broonie/sound because the cleanups there were part of this series and
 all further patches depend on them.
 -----BEGIN PGP SIGNATURE-----
 
 iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAl9NGucQHGtyemtAa2Vy
 bmVsLm9yZwAKCRDBN2bmhouD1zzWD/0T5JdPls++8JUK04hxkunMJO3Ye2ir/a2C
 YAI2M6fbOludcPeGCRnPBZ3uTbeSOXFrV6UuSVi8EVKoAb0EV3G50XGQecmy/TVx
 nq/c90gtnsODL0Kxjm0767WZl9clKaIE3+VNSyQXAhqJqXK8A1L8ovsUpQEj6fr4
 vaNQi6lW7o0r98OEB14M0z59lSWjanUZ33/R22L3AsRihlJTH0Sye2+zVG85LfMD
 5okekSHndt2/NCUxgLTZIkp/cD/pzmhMRZTl1zWvZPPFsbzpuB9wZt46b7vkEzuN
 NgPElEB9AJgyh/28D064lER6TFhz3TcATZjmEIXX+3tYIaoA2lj60QiSejM2FyBk
 U5a0DYAyzwNs4R1GSQxrKnQS1AXQ+yoDniPcyNaSmuZbxaodAs9Hjxg9KfJ2bfs5
 DFfSUJhf1Uam8UYolMbXqSkhd2KQjXpkF0eLK7sGk3wanO+YEqVs777fHpwIPLmd
 767PD0YN+EfDUwmXAJ5Jgv2kvOJIGul7BTgpWtbRHEaDvLHRQl5OhjsWsj9kWCFX
 fx0Jz1sAUqi+gNq3XUFM88/VPEkTgejmVRULnBxqVsar5b/0BeRJEgA6Ljycv0Jv
 2ux5zdMuX/+Xc4zdaJOWaL8NqRuT8nSynKXbWHTzJk4cF3p12/g3q3LOHBBLcLL6
 AzTEA6iZ0w==
 =bjMI
 -----END PGP SIGNATURE-----

Merge tag 'samsung-soc-s3c-5.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/soc

Samsung S3C24xx and S3C64xx machine code cleanup for v5.10

Big cleanup for the Samsung S3C24xx and S3C64xx platforms, although it
also touches files shared with S5Pv210 and Exynos.  This is mostly Arnd
Bergmann work which Krzysztof Kozlowski took over, rebased and polished.

The goal is to cleanup, merge and finally make the Samsung S3C24xx and
S3C64xx architectures multiplatform.  The multiplatform did not happen
yet here - just cleaning up and merging into one arch/arm/mach-s3c
directory.  However this is step forward for multiplatform or at least
to keep this code still maintainable.

This pulls also branch with changes for Samsung SoC sound drivers from
broonie/sound because the cleanups there were part of this series and
all further patches depend on them.

* tag 'samsung-soc-s3c-5.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (62 commits)
  ARM: s3c: Avoid naming clash of S3C24xx and S3C64xx timer setup
  ARM: s3c: Cleanup from old plat-samsung include
  ARM: s3c: make headers local if possible
  ARM: s3c: move into a common directory
  ARM: s3c24xx: stop including mach/hardware.h from mach/io.h
  cpufreq: s3c24xx: move low-level clk reg access into platform code
  cpufreq: s3c2412: use global s3c2412_cpufreq_setrefresh
  ARM: s3c: remove cpufreq header dependencies
  cpufreq: s3c24xx: split out registers
  fbdev: s3c2410fb: remove mach header dependency
  ARM: s3c24xx: bast: avoid irq_desc array usage
  ARM: s3c24xx: spi: avoid hardcoding fiq number in driver
  ARM: s3c24xx: include mach/irqs.h where needed
  ARM: s3c24xx: move s3cmci pinctrl handling into board files
  ARM: s3c24xx: move iis pinctrl config into boards
  ARM: s3c24xx: move spi fiq handler into platform
  ARM: s3c: adc: move header to linux/soc/samsung
  ARM: s3c24xx: move irqchip driver back into platform
  ARM: s3c24xx: move regs-spi.h into spi driver
  ARM: s3c64xx: remove mach/hardware.h
  ...

Link: https://lore.kernel.org/r/20200831154751.7551-1-krzk@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
2020-09-13 11:15:01 -07:00
Peter Ujfalusi
4f02044123 soc: ti: k3-socinfo: Add entry for J7200
Update K3 chipinfo driver to support new TI J7200 SoC.
It's JTAG PARTNO is 0xBB6D.

Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-09-11 21:47:39 -07:00
Grzegorz Jaszczyk
ba59c9b43c soc: ti: pruss: support CORECLK_MUX and IEPCLK_MUX
The IEPCLK_MUX is present on all SoCs whereas the CORECLK_MUX is present
only on AM65x SoCs and J721E. Add support for both these CLK muxes.

This allows the clock rates and clock parents for these to be controlled
through DT leveraging the clk infrastructure for configuring the default
parents and rates.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-09-11 21:47:10 -07:00
Tero Kristo
efa5c01cd7 soc: ti: ti_sci_pm_domains: switch to use multiple genpds instead of one
Current implementation of the genpd support over TI SCI uses a single
genpd across the whole SoC, and attaches multiple devices to this. This
solution has its drawbacks, like it is currently impossible to attach
more than one power domain to a device; the core genpd implementation
requires one genpd per power-domain entry in DT for a single device.
Also, some devices like USB apparently require their own genpd during
probe time, the current shared approach in use does not work at all.

Switch the implementation over to use a single genpd per power domain
entry in DT. The domains are registered with the onecell approach, but
we also add our own xlate service due to recent introduction of the
extended flag for TI SCI PM domains; genpd core xlate service requires
a single cell per powerdomain, but we are using two cells.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-09-11 21:47:08 -07:00
Suman Anna
557003a98f soc: ti: pruss: Enable support for ICSSG subsystems on K3 J721E SoCs
The K3 J721E family of SoCs have a revised version of the PRU-ICSS (ICSSG)
processor subsystem present on K3 AM65x SoCs. These SoCs contain typically
two ICSSG instances named ICSSG0 and ICSSG1. The two ICSSGs are identical
to each other for the most part with minor SoC integration differences and
capabilities. The ICSSG1 supports slightly enhanced features like SGMII
mode Ethernet, while the ICSSG0 instance is limited to MII mode only.

There is no change in the Interrupt Controller w.r.t AM65x. All other
integration aspects are very similar to the ICSSGs on AM65x SoCs.

The existing pruss platform driver has been updated to support these new
ICSSG instances through new J721E specific compatibles.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-09-11 21:43:37 -07:00
Suman Anna
6530cd9b20 soc: ti: pruss: Enable support for ICSSG subsystems on K3 AM65x SoCs
The K3 AM65x family of SoCs have the next generation of the PRU-ICSS
processor subsystem capable of supporting Gigabit Ethernet, and is
commonly referred to as ICSSG. These SoCs contain typically three
ICSSG instances named ICSSG0, ICSSG1 and ICSSG2. The three ICSSGs are
identical to each other for the most part with minor SoC integration
differences and capabilities. The ICSSG2 supports slightly enhanced
features like SGMII mode Ethernet, while the ICSS0 and ICSSG1 instances
are limited to MII mode only.

The ICSSGs on K3 AM65x SoCs are in general super-sets of the PRUSS on the
AM57xx/66AK2G SoCs. They include two additional auxiliary PRU cores called
RTUs and few other additional sub-modules. The interrupt integration is
also different on the K3 AM65x SoCs and are propagated through various
SoC-level Interrupt Router and Interrupt Aggregator blocks. Other IP level
differences include different constant tables, differences in system event
interrupt input sources etc. They also do not have a programmable module
reset line like those present on AM33xx/AM43xx SoCs. The modules are reset
just like any other IP with the SoC's global cold/warm resets.

The existing pruss platform driver has been updated to support these new
ICSSG instances through new AM65x specific compatibles. A build dependency
with ARCH_K3 is added to enable building all the existing PRUSS platform
drivers for this ARMv8 platform.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-09-11 21:43:36 -07:00
Suman Anna
3227c8daac soc: ti: pruss: Add support for PRU-ICSS subsystems on 66AK2G SoC
The 66AK2G SoC supports two PRU-ICSS instances, named PRUSS0 and PRUSS1,
each of which has two PRU processor cores. The two PRU-ICSS instances
are identical to each other with few minor SoC integration differences,
and are very similar to the PRU-ICSS1 of AM57xx/AM43xx. The Shared Data
RAM size is larger and the number of interrupts coming into MPU INTC
is like the instances on AM437x. There are also few other differences
attributing to integration in Keystone architecture (like no SYSCFG
register or PRCM handshake protocols). Other IP level differences
include different constant table, differences in system event interrupt
input sources etc. They also do not have a programmable module reset
line like those present on AM33xx/AM43xx SoCs. The modules are reset
just like any other IP with the SoC's global cold/warm resets.

The existing PRUSS platform driver has been enhanced to support these
66AK2G PRU-ICSS instances through new 66AK2G specific compatible for
properly probing and booting all the different PRU cores in each
PRU-ICSS processor subsystem. A build dependency with ARCH_KEYSTONE
is added to enable the driver to be built in K2G-only configuration.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-09-11 21:43:36 -07:00
Suman Anna
ae19b8a145 soc: ti: pruss: Add support for PRU-ICSS subsystems on AM57xx SoCs
The AM57xx family of SoCs supports two PRU-ICSS instances, each of
which has two PRU processor cores. The two PRU-ICSS instances are
identical to each other, and are very similar to the PRU-ICSS1 of
AM33xx/AM43xx except for a few minor differences like the RAM sizes
and the number of interrupts coming into the MPU INTC. They do
not have a programmable module reset line unlike those present on
AM33xx/AM43xx SoCs. The modules are reset just like any other IP
with the SoC's global cold/warm resets. Each PRU-ICSS's INTC is also
preceded by a Crossbar that enables multiple external events to be
routed to a specific number of input interrupt events. Any interrupt
event directed towards PRUSS needs this crossbar to be setup properly
on the firmware side.

The existing PRUSS platform driver has been enhanced to support
these AM57xx PRU-ICSS instances through new AM57xx specific
compatible for properly probing and booting all the different PRU
cores in each PRU-ICSS processor subsystem. A build dependency with
SOC_DRA7XX is also added to enable the driver to be built in
AM57xx-only configuration (there is no separate Kconfig option
for AM57xx vs DRA7xx).

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-09-11 21:43:35 -07:00
Suman Anna
78251639d3 soc: ti: pruss: Add support for PRU-ICSSs on AM437x SoCs
The AM437x SoCs have two different PRU-ICSS subsystems: PRU-ICSS1
and a smaller PRU-ICSS0. Enhance the PRUSS platform driver to support
both the PRU-ICSS sub-systems on these SoCs.

The PRU-ICSS1 on AM437x is very similar to the PRU-ICSS on AM33xx
except for few minor differences - increased Instruction RAM, increased
Shared Data RAM2, and 1 less interrupt (PRUSS host interrupt 7 which is
redirected to the other PRUSS) towards the MPU INTC. The PRU-ICSS0 is
a cut-down version of the IP, with less DRAM per PRU, no Shared DRAM etc.
It also does not have direct access to L3 bus regions, there is a single
interface to L3 for both PRUSS0 and PRUSS1, and it would have to go
through the PRUSS1's interface. The PRUSS_SYSCFG register is reserved on
PRUSS0, so any external access requires the programming the corresponding
PRUSS_SYSCFG register in PRUSS1. It does have its own dedicated I/O lines
though. Note that this instance does not support any PRU Ethernet related
use cases.

The adaptation uses SoC-specific compatibles in the driver and uses
a newly introduced pruss_match_private_data structure and the
pruss_get_private_data() function to retrieve a PRUSS instance specific
data using a device-name based lookup logic. The reset and the L3 external
access are managed by the parent interconnect ti-sysc bus driver so that
PRUSS1 and PRUSS0 can be independently supported.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-09-11 21:43:35 -07:00
Suman Anna
dc1129564a soc: ti: pruss: Add a platform driver for PRUSS in TI SoCs
The Programmable Real-Time Unit - Industrial Communication
Subsystem (PRU-ICSS) is present on various TI SoCs such as
AM335x or AM437x or the Keystone 66AK2G. Each SoC can have
one or more PRUSS instances that may or may not be identical.
For example, AM335x SoCs have a single PRUSS, while AM437x has
two PRUSS instances PRUSS1 and PRUSS0, with the PRUSS0 being
a cut-down version of the PRUSS1.

The PRUSS consists of dual 32-bit RISC cores called the
Programmable Real-Time Units (PRUs), some shared, data and
instruction memories, some internal peripheral modules, and
an interrupt controller. The programmable nature of the PRUs
provide flexibility to implement custom peripheral interfaces,
fast real-time responses, or specialized data handling.

The PRU-ICSS functionality is achieved through three different
platform drivers addressing a specific portion of the PRUSS.
Some sub-modules of the PRU-ICSS IP reuse some of the existing
drivers (like davinci mdio driver or the generic syscon driver).
This design provides flexibility in representing the different
modules of PRUSS accordingly, and at the same time allowing the
PRUSS driver to add some instance specific configuration within
an SoC.

The PRUSS platform driver deals with the overall PRUSS and is
used for managing the subsystem level resources like various
memories and the CFG module. It is responsible for the creation
and deletion of the platform devices for the child PRU devices
and other child devices (like Interrupt Controller, MDIO node
and some syscon nodes) so that they can be managed by specific
platform drivers. The PRUSS interrupt controller is managed by
an irqchip driver, while the individual PRU RISC cores are
managed by a PRU remoteproc driver.

The driver currently supports the AM335x SoC, and support for
other TI SoCs will be added in subsequent patches.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-09-11 21:43:34 -07:00
Grygorii Strashko
95e7be062a soc: ti: k3: ringacc: add am65x sr2.0 support
The AM65x SR2.0 Ringacc has fixed errata i2023 "RINGACC, UDMA: RINGACC and
UDMA Ring State Interoperability Issue after Channel Teardown". This errata
also fixed for J271E SoC.

Use SOC bus data for K3 SoC identification and enable i2023 errate w/a only
for the AM65x SR1.0. This also makes obsolete "ti,dma-ring-reset-quirk" DT
property.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-09-11 21:34:17 -07:00
Jason Yan
1893a2d526
soc: sunxi: sram: remove unneeded semicolon
Eliminate the following coccicheck warning:

drivers/soc/sunxi/sunxi_sram.c:197:2-3: Unneeded semicolon

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Jason Yan <yanaijie@huawei.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200910140546.1191280-1-yanaijie@huawei.com
2020-09-11 17:02:39 +02:00
Stephen Boyd
2bc20f3c84 soc: qcom: rpmh-rsc: Sleep waiting for tcs slots to be free
The busy loop in rpmh_rsc_send_data() is written with the assumption
that the udelay will be preempted by the tcs_tx_done() irq handler when
the TCS slots are all full. This doesn't hold true when the calling
thread is an irqthread and the tcs_tx_done() irq is also an irqthread.
That's because kernel irqthreads are SCHED_FIFO and thus need to
voluntarily give up priority by calling into the scheduler so that other
threads can run.

I see RCU stalls when I boot with irqthreads on the kernel commandline
because the modem remoteproc driver is trying to send an rpmh async
message from an irqthread that needs to give up the CPU for the rpmh
irqthread to run and clear out tcs slots.

 rcu: INFO: rcu_preempt self-detected stall on CPU
 rcu:     0-....: (1 GPs behind) idle=402/1/0x4000000000000002 softirq=2108/2109 fqs=4920
  (t=21016 jiffies g=2933 q=590)
 Task dump for CPU 0:
 irq/11-smp2p    R  running task        0   148      2 0x00000028
 Call trace:
  dump_backtrace+0x0/0x154
  show_stack+0x20/0x2c
  sched_show_task+0xfc/0x108
  dump_cpu_task+0x44/0x50
  rcu_dump_cpu_stacks+0xa4/0xf8
  rcu_sched_clock_irq+0x7dc/0xaa8
  update_process_times+0x30/0x54
  tick_sched_handle+0x50/0x64
  tick_sched_timer+0x4c/0x8c
  __hrtimer_run_queues+0x21c/0x36c
  hrtimer_interrupt+0xf0/0x22c
  arch_timer_handler_phys+0x40/0x50
  handle_percpu_devid_irq+0x114/0x25c
  __handle_domain_irq+0x84/0xc4
  gic_handle_irq+0xd0/0x178
  el1_irq+0xbc/0x180
  save_return_addr+0x18/0x28
  return_address+0x54/0x88
  preempt_count_sub+0x40/0x88
  _raw_spin_unlock_irqrestore+0x4c/0x6c
  ___ratelimit+0xd0/0x128
  rpmh_rsc_send_data+0x24c/0x378
  __rpmh_write+0x1b0/0x208
  rpmh_write_async+0x90/0xbc
  rpmhpd_send_corner+0x60/0x8c
  rpmhpd_aggregate_corner+0x8c/0x124
  rpmhpd_set_performance_state+0x8c/0xbc
  _genpd_set_performance_state+0xdc/0x1b8
  dev_pm_genpd_set_performance_state+0xb8/0xf8
  q6v5_pds_disable+0x34/0x60 [qcom_q6v5_mss]
  qcom_msa_handover+0x38/0x44 [qcom_q6v5_mss]
  q6v5_handover_interrupt+0x24/0x3c [qcom_q6v5]
  handle_nested_irq+0xd0/0x138
  qcom_smp2p_intr+0x188/0x200
  irq_thread_fn+0x2c/0x70
  irq_thread+0xfc/0x14c
  kthread+0x11c/0x12c
  ret_from_fork+0x10/0x18

This busy loop naturally lends itself to using a wait queue so that each
thread that tries to send a message will sleep waiting on the waitqueue
and only be woken up when a free slot is available. This should make
things more predictable too because the scheduler will be able to sleep
tasks that are waiting on a free tcs instead of the busy loop we
currently have today.

Reviewed-by: Maulik Shah <mkshah@codeaurora.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Maulik Shah <mkshah@codeaurora.org>
Cc: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20200724211711.810009-1-sboyd@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 16:56:12 +00:00
Douglas Anderson
cb8aed7b92 soc: qcom: socinfo: add SC7180 entry to soc_id array
Add an entry for SC7180 SoC.

Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200813080345.1.I85bb28f9ea3fa3bf797ecaf0a5218ced4cfaa6e2@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 16:53:48 +00:00
Kathiravan T
7303fbd2f0 soc: qcom: socinfo: add soc id for IPQ6018
Add the SoC ID for IPQ6018 variant.

Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
Link: https://lore.kernel.org/r/1597645830-30409-1-git-send-email-kathirav@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-10 16:52:45 +00:00
Yoshihiro Shimoda
8e9529f5cd soc: renesas: rcar-rst: Add support for R-Car V3U
Add support for R-Car V3U (R8A779A0) to the R-Car RST driver.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1599470390-29719-12-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-10 17:01:38 +02:00
Yoshihiro Shimoda
090e87e7fb soc: renesas: Identify R-Car V3U
Add support for identifying the R-Car V3U (R8A779A0) SoC.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1599470390-29719-10-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-10 17:01:38 +02:00
Kuninori Morimoto
6d5aded8d5 soc: renesas: Sort driver description title
This patch sorts each driver by description title in alphabetical order.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87a6y2v54o.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-10 17:01:38 +02:00
Kuninori Morimoto
8fae675850 soc: renesas: Use ARM32/ARM64 for menu description
For easy understanding of architecture and alphabetical merging, this
patch uses ARM32/ARM64 for description.
This prepares for sorting the menu.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87bliiv54u.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-10 17:01:38 +02:00
Florian Fainelli
10e7dd54cd soc: bcm: brcmstb: biuctrl: Change RAC data line prefetching after 4 consecutive lines
Change the RACPREFDATA(x) setting to prefetch the next 256-byte line
after 4 consecutive lines have been used, instead of after 2 consecutive
lines. This does improve the synthetic memcpy benchmark by an additional
+0.5% on top of the previous change for Cortex-A72 CPUs.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-09-06 12:43:02 -07:00
Florian Fainelli
091353c88b soc: bcm: brcmstb: biuctrl: Change RAC prefetch distance from +/-1 to +/- 2
Change the RAC prefetch distance from +/- 1 to +/- 2 for Cortex-A72 CPUs
since this provides an average of a 3.8% performance increase for
synthetic memcpy benchmarks.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-09-04 13:48:49 -07:00
Florian Fainelli
4029f3b419 soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72165
72165 uses a Brahma-B53 CPU and its Bus Interface Unit, tune it
according to the existing values we have.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-09-04 13:48:42 -07:00
Florian Fainelli
5dfd145aad soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72164
72164 uses a Brahma-B53 CPU and its Bus Interface Unit, tune it
according to the existing values we have.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-09-04 13:44:32 -07:00
Tony Lindgren
0d7ce5c5c4 Merge branch 'omap-for-v5.10/prm-genpd' into omap-for-v5.10/ti-sysc-drop-pdata 2020-09-03 12:06:18 +03:00