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linux/drivers/phy
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Vidya Sagar 0983529d75 phy: tegra: p2u: Set ENABLE_L2_EXIT_RATE_CHANGE in calibration 
Set ENABLE_L2_EXIT_RATE_CHANGE register bit to request UPHY PLL rate change
to Gen1 during initialization. This helps in the below surprise link down
cases,
  - Surprise link down happens at Gen3/Gen4 link speed.
  - Surprise link down happens and external REFCLK is cut off, which causes
UPHY PLL rate to deviate to an invalid rate.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Link: https://lore.kernel.org/r/20221013183854.21087-9-vidyas@nvidia.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-10-28 17:43:12 +05:30
..
allwinner
phy: move from strlcpy with unused retval to strscpy
2022-08-30 13:12:38 +05:30
amlogic
phy: amlogic: phy-meson-axg-mipi-pcie-analog: Hold reference returned by of_get_parent()
2022-09-20 11:56:38 +05:30
broadcom
arm64: bcmbca: Make BCM4908 drivers depend on ARCH_BCMBCA
2022-08-15 09:55:34 -07:00
cadence
phy: cadence-torrent: Remove unused regmap field from state struct
2022-07-08 10:40:43 +05:30
freescale
phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support
2022-10-17 11:01:03 +05:30
hisilicon
phy: HiSilicon: Fix copy and paste bug in error handling
2021-11-23 10:42:13 +05:30
ingenic
phy: ingenic: Fix a typo in ingenic_usb_phy_probe()
2021-03-30 23:35:17 +05:30
intel
phy: intel: Use dev_err_probe() to simplify code
2022-09-24 12:34:56 +05:30
lantiq
phy: lantiq: rcu-usb2: wait after clock enable
2021-01-13 19:29:03 +05:30
marvell
phy: marvell: phy-mvebu-a3700-comphy: Reset COMPHY registers before USB 3.0 power on
2022-10-17 11:09:34 +05:30
mediatek
phy: phy-mtk-dp: make array driving_params static const
2022-09-29 21:01:27 +05:30
microchip
phy-for-6.1
2022-10-07 16:03:01 -07:00
motorola
treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_30.RULE (part 2)
2022-06-10 14:51:35 +02:00
mscc
…
qualcomm
phy: qcom-qmp-usb: drop power-down delay config
2022-10-28 17:42:29 +05:30
ralink
phy-for-5.14 version 2
2021-06-23 10:33:34 +02:00
renesas
phy: renesas: phy-rcar-gen3-usb2: Add USB2.0 PHY support for RZ/G2L
2021-08-06 18:12:30 +05:30
rockchip
phy: rockchip-snps-pcie3: only look for rockchip,pipe-grf on rk3588
2022-09-29 11:43:04 +05:30
samsung
pci-v5.20-changes
2022-08-04 19:30:35 -07:00
socionext
phy: uniphier-usb3ss: fix unintended writing zeros to PHY register
2021-12-24 10:06:38 +05:30
st
phy: stm32: fix an error code in probe
2022-10-17 10:58:02 +05:30
sunplus
phy: usb: sunplus: Fix return value check in update_disc_vol()
2022-09-13 20:58:33 +05:30
tegra
phy: tegra: p2u: Set ENABLE_L2_EXIT_RATE_CHANGE in calibration
2022-10-28 17:43:12 +05:30
ti
phy: ti: phy-j721e-wiz: add j784s4-wiz-10g module support
2022-10-17 10:59:11 +05:30
xilinx
phy: xilinx: zynqmp: Fix bus width setting for SGMII
2022-01-27 10:55:26 +05:30
Kconfig
phy: usb: Add USB2.0 phy driver for Sunplus SP7021
2022-09-02 21:01:24 +05:30
Makefile
phy: usb: Add USB2.0 phy driver for Sunplus SP7021
2022-09-02 21:01:24 +05:30
phy-can-transceiver.c
phy: phy-can-transceiver: Add support for setting mux
2022-04-11 20:14:10 +05:30
phy-core-mipi-dphy.c
phy: dphy: Correct lpx parameter and its derivatives(ta_{get,go,sure})
2022-02-25 14:14:06 +05:30
phy-core.c
phy: core: Warn when phy_power_on is called before phy_init
2022-04-20 14:45:15 +05:30
phy-lgm-usb.c
phy: Add USB3 PHY support for Intel LGM SoC
2020-09-11 17:12:49 +05:30
phy-lpc18xx-usb-otg.c
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500
2019-06-19 17:09:55 +02:00
phy-pistachio-usb.c
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422
2019-06-05 17:37:15 +02:00
phy-xgene.c
phy: phy-xgene.c: Fix alignment of comment
2021-05-31 14:08:55 +05:30