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linux/drivers/clk/renesas
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Cong Dang 81a7a88a98 clk: renesas: r8a779h0: Add RPC-IF clock 
Add the module clock used by the SPI Multi I/O Bus Controller (RPC-IF)
on the Renesas R-Car V4M (R8A779H0) SoC.

Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/07a72378ca64b44341af960f042a6efd41d10dc3.1708354355.git.geert+renesas@glider.be
2024-02-20 11:37:34 +01:00
..
clk-div6.c
clk: renesas: div6: Implement range checking
2021-05-11 09:58:13 +02:00
clk-div6.h
We have two changes to the core framework this time around. The first being a
2017-11-17 20:04:24 -08:00
clk-emev2.c
clk: renesas: emev2: Remove obsolete clkdev registration
2023-07-27 14:32:41 +02:00
clk-mstp.c
clk: renesas: mstp: Remove obsolete clkdev registration
2024-01-23 21:23:47 +01:00
clk-r8a73a4.c
clk: renesas: r8a73a4: Remove r8a73a4_cpg.reg
2022-06-13 11:53:18 +02:00
clk-r8a7740.c
clk: renesas: r8a7740: Remove r8a7740_cpg.reg
2022-06-13 11:53:18 +02:00
clk-r8a7778.c
clk: renesas: r8a7778: Remove struct r8a7778_cpg
2022-06-13 11:53:18 +02:00
clk-r8a7779.c
clk: renesas: r8a7779: Remove struct r8a7779_cpg
2022-06-13 11:53:18 +02:00
clk-rz.c
clk: renesas: rza1: Remove struct rz_cpg
2022-06-13 11:53:18 +02:00
clk-sh73a0.c
clk: renesas: sh73a0: Remove sh73a0_cpg.reg
2022-06-13 11:53:18 +02:00
Kconfig
clk: renesas: cpg-mssr: Add support for R-Car V4M
2024-01-31 11:19:21 +01:00
Makefile
clk: renesas: cpg-mssr: Add support for R-Car V4M
2024-01-31 11:19:21 +01:00
r7s9210-cpg-mssr.c
clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag
2020-09-17 15:30:08 +02:00
r8a774a1-cpg-mssr.c
clk: renesas: rcar-gen3: Add ADG clocks
2023-08-15 11:34:43 +02:00
r8a774b1-cpg-mssr.c
clk: renesas: rcar-gen3: Add ADG clocks
2023-08-15 11:34:43 +02:00
r8a774c0-cpg-mssr.c
clk: renesas: rcar-gen3: Add ADG clocks
2023-08-15 11:34:43 +02:00
r8a774e1-cpg-mssr.c
clk: renesas: rcar-gen3: Add ADG clocks
2023-08-15 11:34:43 +02:00
r8a779a0-cpg-mssr.c
clk: renesas: r8a779a0: Add PWM clock
2023-05-08 09:14:33 +02:00
r8a779f0-cpg-mssr.c
clk: renesas: r8a779f0: Correct PFC/GPIO parent clock
2024-02-13 17:13:25 +01:00
r8a779g0-cpg-mssr.c
clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks
2024-02-13 17:10:26 +01:00
r8a779h0-cpg-mssr.c
clk: renesas: r8a779h0: Add RPC-IF clock
2024-02-20 11:37:34 +01:00
r8a7742-cpg-mssr.c
clk: renesas: r8a7742: Add clk entry for VSPR
2020-09-04 09:42:01 +02:00
r8a7743-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7745-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7790-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7791-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7792-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7794-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7795-cpg-mssr.c
clk: renesas: r8a7795: Constify r8a7795_*_clks
2023-09-26 09:38:00 +02:00
r8a7796-cpg-mssr.c
clk: renesas: rcar-gen3: Add ADG clocks
2023-08-15 11:34:43 +02:00
r8a77470-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a77965-cpg-mssr.c
clk: renesas: rcar-gen3: Add ADG clocks
2023-08-15 11:34:43 +02:00
r8a77970-cpg-mssr.c
clk: renesas: r8a77970: Add Z2 clock
2023-03-10 17:07:07 +01:00
r8a77980-cpg-mssr.c
clk: renesas: r8a77980: Add I2C5 clock
2023-03-30 16:44:04 +02:00
r8a77990-cpg-mssr.c
clk: renesas: rcar-gen3: Add ADG clocks
2023-08-15 11:34:43 +02:00
r8a77995-cpg-mssr.c
clk: renesas: rcar-gen3: Add ADG clocks
2023-08-15 11:34:43 +02:00
r9a06g032-clocks.c
clk: renesas: r9a06g032: Name anonymous structs
2023-09-18 10:05:23 +02:00
r9a07g043-cpg.c
clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable
2024-02-13 17:13:25 +01:00
r9a07g044-cpg.c
clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable
2024-02-13 17:13:25 +01:00
r9a08g045-cpg.c
clk: renesas: r9a08g045: Add clock and reset support for watchdog
2024-01-31 11:14:53 +01:00
r9a09g011-cpg.c
clk: renesas: r9a09g011: Add CSI related clocks
2023-07-10 09:31:53 +02:00
rcar-cpg-lib.c
clk: renesas: rcar-gen3: Extend SDnH divider table
2023-10-05 13:44:34 +02:00
rcar-cpg-lib.h
clk: renesas: rcar-gen3: Switch to new SD clock handling
2021-11-19 11:32:39 +01:00
rcar-gen2-cpg.c
clk: renesas: Zero init clk_init_data
2021-03-30 09:58:27 +02:00
rcar-gen2-cpg.h
clk: renesas: rcar-gen2: Change multipliers and dividers to u8
2019-12-10 10:24:10 +01:00
rcar-gen3-cpg.c
clk: renesas: rcar-gen3: Add support for ZG clock
2023-07-10 09:31:29 +02:00
rcar-gen3-cpg.h
clk: renesas: rcar-gen3: Add support for ZG clock
2023-07-10 09:31:29 +02:00
rcar-gen4-cpg.c
clk: renesas: rcar-gen4: Add support for FRQCRC1
2024-01-31 11:19:21 +01:00
rcar-gen4-cpg.h
clk: renesas: r8a779g0: Add custom clock for PLL2
2023-01-24 10:11:50 +01:00
rcar-usb2-clock-sel.c
clk: Explicitly include correct DT includes
2023-07-19 13:13:16 -07:00
renesas-cpg-mssr.c
clk: renesas: cpg-mssr: Add support for R-Car V4M
2024-01-31 11:19:21 +01:00
renesas-cpg-mssr.h
clk: renesas: cpg-mssr: Add support for R-Car V4M
2024-01-31 11:19:21 +01:00
rzg2l-cpg.c
clk: renesas: rzg2l: Check reset monitor registers
2023-12-13 20:05:36 +01:00
rzg2l-cpg.h
clk: renesas: Add minimal boot support for RZ/G3S SoC
2023-10-10 09:29:48 +02:00