José Roberto de Souza 26e5378d11 drm/i915/psr: Cache sink synchronization latency
This value do not change overtime so better cache it than
fetch it every PSR enable.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180328223046.16125-8-jose.souza@intel.com
2018-03-30 10:18:09 -07:00
..
2017-12-21 14:52:36 +01:00