José Roberto de Souza 26e5378d11 drm/i915/psr: Cache sink synchronization latency
This value do not change overtime so better cache it than
fetch it every PSR enable.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180328223046.16125-8-jose.souza@intel.com
2018-03-30 10:18:09 -07:00
..
2018-01-30 18:05:25 +01:00
2018-02-01 11:35:46 +10:00
2018-02-06 09:59:40 -08:00
2018-02-16 09:29:27 +10:00
2018-02-16 09:29:27 +10:00
2017-12-27 19:00:09 -05:00
2018-02-23 11:12:52 +10:00
2018-02-19 14:19:04 -05:00
2017-11-15 20:42:10 -08:00
2018-02-19 14:19:52 -05:00
2018-02-16 09:29:27 +10:00
2018-02-16 09:29:27 +10:00
2017-12-19 21:37:24 +10:00
2017-12-19 21:37:24 +10:00
2017-11-23 12:31:49 +02:00
2017-11-15 20:42:10 -08:00
2018-01-25 11:42:25 +10:00
2018-01-24 15:49:04 -05:00