Dan Williams 2901c8bded cxl/region: Fix decoder interleave programming ... Jonathan notes: "Curiously interleave ways = 1 for the EPs which is obviously wrong" ...while testing the latest CXL development branch on QEMU. It turns out the region creation process failed to program the endpoint decoders. This was missed because the default settings of x1 at 4K intereleave still results in the region appearing to function. Jonathan caught the bug by reverse mapping the translations that need to happen for the QEMU support. Link: https://lore.kernel.org/r/62e95fdf9f6e2_30440294e4@dwillia2-xfh.jf.intel.com.notmuch Fixes: 384e624bb2 ("cxl/region: Attach endpoint decoders") Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/165951146336.967013.11160153960900111443.stgit@dwillia2-xfh.jf.intel.com Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>		2022-08-05 08:41:19 -07:00
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core	cxl/region: Fix decoder interleave programming	2022-08-05 08:41:19 -07:00
acpi.c	cxl/acpi: Minimize granularity for x1 interleaves	2022-08-01 15:36:33 -07:00
cxl.h	cxl/region: describe targets and nr_targets members of cxl_region_params	2022-08-05 08:41:02 -07:00
cxlmem.h	cxl/region: Attach endpoint decoders	2022-07-25 12:18:07 -07:00
cxlpci.h	cxl/port: Read CDAT table	2022-07-19 15:38:05 -07:00
Kconfig	cxl/region: Allocate HPA capacity to regions	2022-07-25 12:18:06 -07:00
Makefile	PM: CXL: Disable suspend	2022-04-22 16:09:42 -07:00
mem.c	cxl/mem: Enumerate port targets before adding endpoints	2022-07-21 17:19:25 -07:00
pci.c	cxl/pci: Create PCI DOE mailbox's for memory devices	2022-07-19 15:38:04 -07:00
pmem.c	cxl/region: Fix IS_ERR() vs NULL check	2022-08-05 08:41:02 -07:00
port.c	cxl/port: Read CDAT table	2022-07-19 15:38:05 -07:00