42b89447b6
Conor Dooley <conor@kernel.org> says: From: Conor Dooley <conor.dooley@microchip.com> Here are some bits that were discussed with Drew on the "should we allow caps" threads that I have now created patches for: - splitting of riscv_of_processor_hartid() into two distinct functions, one for use purely during early boot, prior to the establishment of the possible-cpus mask & another to fit the other current use-cases - that then allows us to then completely skip some validation of the hartid in the parser - the biggest diff in the series is a rework of the comments in the parser, as I have mostly found the existing (sparse) ones to not be all that helpful whenever I have to go back and look at it - from writing the comments, I found a conditional doing a bit of a dance that I found counter-intuitive, so I've had a go at making that match what I would expect a little better - `i` implies 4 other extensions, so add them as extensions and set them for the craic. Sure why not like... * b4-shazam-merge: RISC-V: always report presence of extensions formerly part of the base ISA dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support RISC-V: remove decrement/increment dance in ISA string parser RISC-V: rework comments in ISA string parser RISC-V: validate riscv,isa at boot, not during ISA string parsing RISC-V: split early & late of_node to hartid mapping RISC-V: simplify register width check in ISA string parsing Link: https://lore.kernel.org/r/20230607-audacity-overhaul-82bb867a825f@spud Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
100 lines
2.7 KiB
C
100 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_PROCESSOR_H
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#define _ASM_RISCV_PROCESSOR_H
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#include <linux/const.h>
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#include <linux/cache.h>
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#include <vdso/processor.h>
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#include <asm/ptrace.h>
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/*
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* This decides where the kernel will search for a free chunk of vm
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* space during mmap's.
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*/
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#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
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#define STACK_TOP TASK_SIZE
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#ifdef CONFIG_64BIT
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#define STACK_TOP_MAX TASK_SIZE_64
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#else
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#define STACK_TOP_MAX TASK_SIZE
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#endif
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#define STACK_ALIGN 16
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#ifndef __ASSEMBLY__
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struct task_struct;
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struct pt_regs;
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/* CPU-specific state of a task */
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struct thread_struct {
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/* Callee-saved registers */
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unsigned long ra;
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unsigned long sp; /* Kernel mode stack */
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unsigned long s[12]; /* s[0]: frame pointer */
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struct __riscv_d_ext_state fstate;
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unsigned long bad_cause;
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unsigned long vstate_ctrl;
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struct __riscv_v_ext_state vstate;
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};
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/* Whitelist the fstate from the task_struct for hardened usercopy */
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static inline void arch_thread_struct_whitelist(unsigned long *offset,
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unsigned long *size)
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{
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*offset = offsetof(struct thread_struct, fstate);
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*size = sizeof_field(struct thread_struct, fstate);
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}
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#define INIT_THREAD { \
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.sp = sizeof(init_stack) + (long)&init_stack, \
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}
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#define task_pt_regs(tsk) \
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((struct pt_regs *)(task_stack_page(tsk) + THREAD_SIZE \
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- ALIGN(sizeof(struct pt_regs), STACK_ALIGN)))
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#define KSTK_EIP(tsk) (task_pt_regs(tsk)->epc)
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#define KSTK_ESP(tsk) (task_pt_regs(tsk)->sp)
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/* Do necessary setup to start up a newly executed thread. */
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extern void start_thread(struct pt_regs *regs,
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unsigned long pc, unsigned long sp);
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extern unsigned long __get_wchan(struct task_struct *p);
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static inline void wait_for_interrupt(void)
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{
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__asm__ __volatile__ ("wfi");
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}
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struct device_node;
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int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid);
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int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hartid);
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int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid);
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extern void riscv_fill_hwcap(void);
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extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
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extern unsigned long signal_minsigstksz __ro_after_init;
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#ifdef CONFIG_RISCV_ISA_V
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/* Userspace interface for PR_RISCV_V_{SET,GET}_VS prctl()s: */
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#define RISCV_V_SET_CONTROL(arg) riscv_v_vstate_ctrl_set_current(arg)
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#define RISCV_V_GET_CONTROL() riscv_v_vstate_ctrl_get_current()
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extern long riscv_v_vstate_ctrl_set_current(unsigned long arg);
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extern long riscv_v_vstate_ctrl_get_current(void);
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#endif /* CONFIG_RISCV_ISA_V */
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_RISCV_PROCESSOR_H */
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