Michal Simek 3880c39a80 ARM: zynq: Rename bus to be align with simple-bus yaml
Rename amba to AXI. Based on Xilinx Zynq TRM (Chapter 5) chip is "AXI
point-to-point channels for communicating addresses, data, and response
transactions between master and slave clients. This ARM AMBA 3.0..."

Issues are reported as:
.. amba: $nodename:0: 'amba' does not match
'^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'
>From schema:
../github.com/devicetree-org/dt-schema/dtschema/schemas/simple-bus.yaml

Similar change has been done for Xilinx ZynqMP SoC.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/8a4bc80debfbb79c296e76fc1e4c173e62657286.1606397101.git.michal.simek@xilinx.com
2020-12-09 15:18:27 +01:00
..
2020-10-24 10:44:18 -07:00
2020-10-24 10:44:18 -07:00
2020-08-03 19:19:34 -07:00
2020-08-03 19:19:34 -07:00
2020-08-03 19:19:34 -07:00
2020-10-24 10:44:18 -07:00
2020-10-24 10:44:18 -07:00
2020-09-03 10:09:34 +02:00
2020-10-24 10:44:18 -07:00
2020-10-24 10:44:18 -07:00
2020-10-24 10:44:18 -07:00
2020-06-04 19:47:11 -07:00
2020-10-24 10:44:18 -07:00
2020-03-20 23:20:26 +01:00
2020-10-24 10:44:18 -07:00
2020-10-24 10:44:18 -07:00
2020-08-03 19:19:34 -07:00
2020-08-17 16:06:01 +08:00
2020-08-17 16:06:33 +08:00
2020-02-08 13:58:44 -08:00
2020-08-17 16:06:36 +08:00
2020-10-24 10:44:18 -07:00
2020-11-26 14:16:08 +01:00
2020-07-22 22:05:17 +02:00
2020-07-22 22:05:22 +02:00
2020-09-07 10:54:08 +01:00
2020-10-03 12:56:56 -07:00
2020-01-13 10:11:40 -08:00
2020-10-24 10:44:18 -07:00
2020-10-24 10:33:08 -07:00
2020-06-04 20:02:14 -07:00
2020-06-04 20:02:14 -07:00
2020-10-24 10:44:18 -07:00
2020-09-30 14:15:18 +08:00
2020-08-03 19:19:34 -07:00
2020-02-17 14:39:34 +08:00
2020-11-26 14:16:08 +01:00