73106f75bf
Meson6, Meson8, Meson8b and Meson8m2 are using a similar SDHC controller IP which typically connects to an eMMC chip (because unlike the SDIO controller the SDHC controller has an 8-bit bus interface). On Meson8, Meson8b and Meson8m2 the clock inputs are all the same. However, Meson8m2 seems to have an improved version of the SHDC controller IP which doesn't require the driver to wait manually for a flush of a DMA transfer. Thus every SoC has it's own compatible string so if more difference are discovered they can be implemented. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200620163654.37207-2-martin.blumenstingl@googlemail.com
102 lines
2.3 KiB
Plaintext
102 lines
2.3 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
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*/
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#include "meson8.dtsi"
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/ {
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model = "Amlogic Meson8m2 SoC";
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compatible = "amlogic,meson8m2";
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}; /* end of / */
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&clkc {
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compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc";
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};
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&dmcbus {
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/* the offset of the canvas registers has changed compared to Meson8 */
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/delete-node/ video-lut@20;
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canvas: video-lut@48 {
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compatible = "amlogic,meson8m2-canvas", "amlogic,canvas";
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reg = <0x48 0x14>;
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};
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};
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ðmac {
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compatible = "amlogic,meson8m2-dwmac", "snps,dwmac";
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reg = <0xc9410000 0x10000
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0xc1108140 0x8>;
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clocks = <&clkc CLKID_ETH>,
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<&clkc CLKID_MPLL2>,
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<&clkc CLKID_MPLL2>,
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<&clkc CLKID_FCLK_DIV2>;
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clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
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resets = <&reset RESET_ETHERNET>;
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reset-names = "stmmaceth";
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};
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&pinctrl_aobus {
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compatible = "amlogic,meson8m2-aobus-pinctrl",
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"amlogic,meson8-aobus-pinctrl";
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};
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&pinctrl_cbus {
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compatible = "amlogic,meson8m2-cbus-pinctrl",
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"amlogic,meson8-cbus-pinctrl";
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eth_rgmii_pins: ethernet {
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mux {
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groups = "eth_tx_clk_50m", "eth_tx_en",
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"eth_txd3", "eth_txd2",
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"eth_txd1", "eth_txd0",
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"eth_rx_clk_in", "eth_rx_dv",
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"eth_rxd3", "eth_rxd2",
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"eth_rxd1", "eth_rxd0",
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"eth_mdio", "eth_mdc";
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function = "ethernet";
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bias-disable;
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};
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};
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};
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&pwrc {
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compatible = "amlogic,meson8m2-pwrc";
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resets = <&reset RESET_DBLK>,
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<&reset RESET_PIC_DC>,
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<&reset RESET_HDMI_APB>,
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<&reset RESET_HDMI_SYSTEM_RESET>,
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<&reset RESET_VENCI>,
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<&reset RESET_VENCP>,
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<&reset RESET_VDAC_4>,
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<&reset RESET_VENCL>,
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<&reset RESET_VIU>,
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<&reset RESET_VENC>,
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<&reset RESET_RDMA>;
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reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", "venci",
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"vencp", "vdac", "vencl", "viu", "venc", "rdma";
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assigned-clocks = <&clkc CLKID_VPU>;
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assigned-clock-rates = <364000000>;
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};
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&saradc {
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compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc";
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};
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&sdhc {
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compatible = "amlogic,meson8m2-sdhc", "amlogic,meson-mx-sdhc";
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};
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&usb0_phy {
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compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy";
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};
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&usb1_phy {
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compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy";
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};
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&wdt {
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compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt";
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};
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