06c0dd96bf
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
112 lines
2.9 KiB
C
112 lines
2.9 KiB
C
/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "msm_drv.h"
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#include "mdp5_kms.h"
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void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask)
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{
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mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_EN, irqmask);
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}
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static void mdp5_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus)
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{
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DRM_ERROR("errors: %08x\n", irqstatus);
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}
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void mdp5_irq_preinstall(struct msm_kms *kms)
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{
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struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
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mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0xffffffff);
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}
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int mdp5_irq_postinstall(struct msm_kms *kms)
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{
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struct mdp_kms *mdp_kms = to_mdp_kms(kms);
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struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
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struct mdp_irq *error_handler = &mdp5_kms->error_handler;
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error_handler->irq = mdp5_irq_error_handler;
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error_handler->irqmask = MDP5_IRQ_INTF0_UNDER_RUN |
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MDP5_IRQ_INTF1_UNDER_RUN |
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MDP5_IRQ_INTF2_UNDER_RUN |
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MDP5_IRQ_INTF3_UNDER_RUN;
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mdp_irq_register(mdp_kms, error_handler);
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return 0;
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}
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void mdp5_irq_uninstall(struct msm_kms *kms)
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{
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struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
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mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000);
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}
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static void mdp5_irq_mdp(struct mdp_kms *mdp_kms)
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{
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struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
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struct drm_device *dev = mdp5_kms->dev;
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struct msm_drm_private *priv = dev->dev_private;
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unsigned int id;
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uint32_t status;
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status = mdp5_read(mdp5_kms, REG_MDP5_INTR_STATUS);
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mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, status);
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VERB("status=%08x", status);
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for (id = 0; id < priv->num_crtcs; id++)
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if (status & mdp5_crtc_vblank(priv->crtcs[id]))
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drm_handle_vblank(dev, id);
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mdp_dispatch_irqs(mdp_kms, status);
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}
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irqreturn_t mdp5_irq(struct msm_kms *kms)
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{
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struct mdp_kms *mdp_kms = to_mdp_kms(kms);
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struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
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uint32_t intr;
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intr = mdp5_read(mdp5_kms, REG_MDP5_HW_INTR_STATUS);
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VERB("intr=%08x", intr);
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if (intr & MDP5_HW_INTR_STATUS_INTR_MDP)
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mdp5_irq_mdp(mdp_kms);
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if (intr & MDP5_HW_INTR_STATUS_INTR_HDMI)
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hdmi_irq(0, mdp5_kms->hdmi);
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return IRQ_HANDLED;
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}
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int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
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{
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mdp_update_vblank_mask(to_mdp_kms(kms),
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mdp5_crtc_vblank(crtc), true);
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return 0;
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}
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void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
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{
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mdp_update_vblank_mask(to_mdp_kms(kms),
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mdp5_crtc_vblank(crtc), false);
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}
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