4ebd92d2e2
zynqmp_clk_divider_round_rate() returns actual divider value after calculating from parent rate and desired rate, even though that rate is not supported by single divider of hardware. It is also possible that such divisor value can be achieved through 2 different dividers. As, Linux tries to set such divisor value(out of range) in single divider set divider is getting failed. Fix the same by computing best possible combination of two divisors which provides more accurate clock rate. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Link: https://lkml.kernel.org/r/1575527759-26452-6-git-send-email-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
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| .. | ||
| clk-gate-zynqmp.c | ||
| clk-mux-zynqmp.c | ||
| clk-zynqmp.h | ||
| clkc.c | ||
| divider.c | ||
| Kconfig | ||
| Makefile | ||
| pll.c | ||