Archit Taneja ff73ff1940 drm/msm/dsi: Populate the 10nm PHY funcs ...

Populate the PHY ops with the downstream driver as reference.

There are a couple of TODOs which need to be resolved:
- The PHY timings are all hardcoded for now. This needs to be replaced
  with automatic calculations once we get/understand them.
- There are some lane configuration registers which use a new
  representation between physical and logical lane mappings. For now,
  we've hardcoced them to follow the default mapping (i.e
  logical 0 -> phy 0, logical 1 -> phy 1 etc).

Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

2018-02-20 10:41:21 -05:00

..

dsi_phy_10nm.c

drm/msm/dsi: Populate the 10nm PHY funcs

2018-02-20 10:41:21 -05:00

dsi_phy_14nm.c

drm/msm/dsi: Add PHY/PLL for 8x96

2017-02-06 11:28:45 -05:00

dsi_phy_20nm.c

drm/msm/dsi: Move PHY operations out of host

2017-02-06 11:28:45 -05:00

dsi_phy_28nm_8960.c

drm/msm/dsi: Move PHY operations out of host

2017-02-06 11:28:45 -05:00

dsi_phy_28nm.c

drm/msm/dsi: Move PHY operations out of host

2017-02-06 11:28:45 -05:00

dsi_phy.c

drm/msm/dsi: Add skeleton 10nm PHY/PLL code

2018-02-20 10:41:20 -05:00

dsi_phy.h

drm/msm/dsi: Add skeleton 10nm PHY/PLL code

2018-02-20 10:41:20 -05:00