linux/drivers/clk/socfpga
Colin Ian King 52d1a8da40 clk: socfpga: remove redundant initialization of variable div
The variable div is being initialized with a value that is
never read and it is being updated later with a new value.  The
initialization is redundant and can be removed.

Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Link: https://lore.kernel.org/r/20210406182746.432861-1-colin.king@canonical.com
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-04-07 16:30:23 -07:00
..
clk-agilex.c clk: socfpga: Fix code formatting 2021-03-30 19:31:26 -07:00
clk-gate-a10.c clk: socfpga: arria10: Fix memory leak of socfpga_clk on error return 2021-04-07 16:29:31 -07:00
clk-gate-s10.c clk: socfpga: remove redundant initialization of variable div 2021-04-07 16:30:23 -07:00
clk-gate.c clk: socfpga: use clk_hw_register for a5/c5 2021-03-30 19:26:26 -07:00
clk-periph-a10.c clk: socfpga: arria10: convert to use clk_hw 2021-03-30 19:26:26 -07:00
clk-periph-s10.c clk: socfpga: Convert to s10/agilex/n5x to use clk_hw 2021-03-30 19:26:26 -07:00
clk-periph.c clk: socfpga: use clk_hw_register for a5/c5 2021-03-30 19:26:26 -07:00
clk-pll-a10.c clk: socfpga: arria10: convert to use clk_hw 2021-03-30 19:26:26 -07:00
clk-pll-s10.c clk: socfpga: remove redundant initialization of variable div 2021-04-07 16:30:23 -07:00
clk-pll.c clk: socfpga: use clk_hw_register for a5/c5 2021-03-30 19:26:26 -07:00
clk-s10.c clk: socfpga: Convert to s10/agilex/n5x to use clk_hw 2021-03-30 19:26:26 -07:00
clk.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13 2019-05-21 11:28:45 +02:00
clk.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288 2019-06-05 17:36:37 +02:00
Makefile clk: socfpga: agilex: add clock driver for the Agilex platform 2020-05-26 19:13:05 -07:00
stratix10-clk.h clk: socfpga: Convert to s10/agilex/n5x to use clk_hw 2021-03-30 19:26:26 -07:00