Ben Widawsky 53fa1bff34 cxl/core: Track port depth ... In preparation for proving CXL subsystem usage of the device_lock() order track the depth of ports with the expectation that shallower port locks can be held over deeper port locks. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/164298419321.3018233.4469731547378993606.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>		2022-02-08 22:57:29 -08:00
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core	cxl/core: Track port depth	2022-02-08 22:57:29 -08:00
acpi.c	cxl/core/port: Make passthrough decoder init implicit	2022-02-08 22:57:29 -08:00
cxl.h	cxl/core: Track port depth	2022-02-08 22:57:29 -08:00
cxlmem.h	cxl/memdev: Remove unused cxlmd field	2021-11-15 11:02:59 -08:00
Kconfig	cxl: Rename CXL_MEM to CXL_PCI	2022-02-08 22:57:27 -08:00
Makefile	cxl: Rename CXL_MEM to CXL_PCI	2022-02-08 22:57:27 -08:00
pci.c	cxl/acpi: Map component registers for Root Ports	2022-02-08 22:57:28 -08:00
pci.h	cxl/acpi: Map component registers for Root Ports	2022-02-08 22:57:28 -08:00
pmem.c	cxl/pmem: Fix module reload vs workqueue state	2021-11-15 11:03:00 -08:00