linux/drivers/cxl/core
Ben Widawsky 53fa1bff34 cxl/core: Track port depth
In preparation for proving CXL subsystem usage of the device_lock()
order track the depth of ports with the expectation that  shallower port
locks can be held over deeper port locks.

Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/164298419321.3018233.4469731547378993606.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2022-02-08 22:57:29 -08:00
..
core.h cxl/core: Split decoder setup into alloc + add 2021-09-21 14:09:34 -07:00
Makefile cxl/core/port: Rename bus.c to port.c 2022-02-08 22:57:28 -08:00
mbox.c cxl/core: Convert to EXPORT_SYMBOL_NS_GPL 2021-11-15 11:02:59 -08:00
memdev.c cxl/core: Convert to EXPORT_SYMBOL_NS_GPL 2021-11-15 11:02:59 -08:00
pmem.c cxl/pmem: Fix module reload vs workqueue state 2021-11-15 11:03:00 -08:00
port.c cxl/core: Track port depth 2022-02-08 22:57:29 -08:00
regs.c cxl/core: Fix cxl_probe_component_regs() error message 2022-02-08 22:57:28 -08:00