Will Deacon 5ef3fe4cec arm64: Avoid redundant type conversions in xchg() and cmpxchg() ...

Our atomic instructions (either LSE atomics of LDXR/STXR sequences)
natively support byte, half-word, word and double-word memory accesses
so there is no need to mask the data register prior to being stored.

Signed-off-by: Will Deacon <will.deacon@arm.com>

2018-12-07 17:27:55 +00:00

..

asm

arm64: Avoid redundant type conversions in xchg() and cmpxchg()

2018-12-07 17:27:55 +00:00

uapi/asm

arm64: Add support for SB barrier and patch in over DSB; ISB sequences

2018-12-06 16:47:04 +00:00