e0e3aca997
This is copy/pasta that breaks modular builds. Fix the match table to use the right pointer, or the right device table type. And while we're including the header, fix the order to be linux, dt-bindings, and finally local. Cc: Garmin.Chang <Garmin.Chang@mediatek.com> Cc: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Fixes:f42b9e9a43("clk: mediatek: Add MT8188 wpesys clock support") Fixes:0d2f2cefba("clk: mediatek: Add MT8188 adsp clock support") Fixes:e4aaa60eae("clk: mediatek: Add MT8188 vdosys0 clock support") Fixes:cfa4609f9b("clk: mediatek: Add MT8188 vdosys1 clock support") Fixes:bb87c1109c("clk: mediatek: Add MT8188 vencsys clock support") Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/oe-kbuild-all/202304011039.UBDX1UOT-lkp@intel.com/ Link: https://lore.kernel.org/oe-kbuild-all/202304020649.QO2HlpD5-lkp@intel.com/ Link: https://lore.kernel.org/oe-kbuild-all/202304021055.WDhQPcoS-lkp@intel.com/ Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20230404204553.1256263-1-sboyd@kernel.org
83 lines
2.6 KiB
C
83 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Garmin Chang <garmin.chang@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/mediatek,mt8188-clk.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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static const struct mtk_gate_regs imp_iic_wrap_cg_regs = {
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.set_ofs = 0xe08,
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.clr_ofs = 0xe04,
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.sta_ofs = 0xe00,
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};
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#define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift) \
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GATE_MTK_FLAGS(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift, \
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&mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
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static const struct mtk_gate imp_iic_wrap_c_clks[] = {
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GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0,
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"imp_iic_wrap_c_ap_clock_i2c0", "top_i2c", 0),
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GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2,
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"imp_iic_wrap_c_ap_clock_i2c2", "top_i2c", 1),
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GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3,
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"imp_iic_wrap_c_ap_clock_i2c3", "top_i2c", 2),
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};
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static const struct mtk_gate imp_iic_wrap_w_clks[] = {
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GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1,
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"imp_iic_wrap_w_ap_clock_i2c1", "top_i2c", 0),
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GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4,
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"imp_iic_wrap_w_ap_clock_i2c4", "top_i2c", 1),
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};
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static const struct mtk_gate imp_iic_wrap_en_clks[] = {
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GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5,
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"imp_iic_wrap_en_ap_clock_i2c5", "top_i2c", 0),
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GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6,
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"imp_iic_wrap_en_ap_clock_i2c6", "top_i2c", 1),
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};
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static const struct mtk_clk_desc imp_iic_wrap_c_desc = {
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.clks = imp_iic_wrap_c_clks,
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.num_clks = ARRAY_SIZE(imp_iic_wrap_c_clks),
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};
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static const struct mtk_clk_desc imp_iic_wrap_w_desc = {
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.clks = imp_iic_wrap_w_clks,
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.num_clks = ARRAY_SIZE(imp_iic_wrap_w_clks),
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};
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static const struct mtk_clk_desc imp_iic_wrap_en_desc = {
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.clks = imp_iic_wrap_en_clks,
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.num_clks = ARRAY_SIZE(imp_iic_wrap_en_clks),
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};
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static const struct of_device_id of_match_clk_mt8188_imp_iic_wrap[] = {
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{ .compatible = "mediatek,mt8188-imp-iic-wrap-c", .data = &imp_iic_wrap_c_desc },
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{ .compatible = "mediatek,mt8188-imp-iic-wrap-w", .data = &imp_iic_wrap_w_desc },
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{ .compatible = "mediatek,mt8188-imp-iic-wrap-en", .data = &imp_iic_wrap_en_desc },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_imp_iic_wrap);
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static struct platform_driver clk_mt8188_imp_iic_wrap_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8188-imp_iic_wrap",
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.of_match_table = of_match_clk_mt8188_imp_iic_wrap,
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},
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};
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module_platform_driver(clk_mt8188_imp_iic_wrap_drv);
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MODULE_LICENSE("GPL");
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