Elaine Zhang 64a1644bc3 clk: rockchip: fix the rv1108 clk_mac sel register description
The source clock ordering is wrong, as shown in the TRM:
cru_sel24_con[8]
rmii_extclk_sel
clock source select control register
1'b0: from internal PLL
1'b1: from external IO

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-08-22 02:55:03 +02:00
..
2017-06-19 17:14:11 -07:00
2016-12-15 15:39:02 -08:00
2016-11-16 11:19:20 -08:00
2017-06-15 10:48:08 +03:00
2017-06-19 19:02:42 -07:00
2017-06-02 15:37:45 -07:00
2016-11-09 12:05:50 -08:00
2016-10-23 10:18:45 -07:00