Andrew Jeffery 801b787a69 clk: aspeed: Add RMII RCLK gates for both AST2500 MACs
RCLK is a fixed 50MHz clock derived from HPLL that is described by a
single gate for each MAC.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lkml.kernel.org/r/20191010020655.3776-3-andrew@aj.id.au
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-26 10:02:48 -08:00
..
2019-09-22 09:39:09 -07:00
2019-09-24 15:54:11 -07:00
2019-09-30 10:04:28 -07:00
2019-09-29 19:25:39 -07:00
2019-09-22 09:30:30 -07:00
2019-09-22 09:30:30 -07:00
2019-09-22 09:39:09 -07:00
2019-09-19 14:14:28 -07:00
2019-09-30 10:04:28 -07:00
2019-09-18 11:14:31 -07:00
2019-09-27 12:19:47 -07:00
2019-09-27 11:13:35 -07:00
2019-09-22 12:02:21 -07:00
2019-09-29 11:20:41 -07:00
2019-09-28 20:44:12 +02:00
2019-09-19 14:14:28 -07:00
2019-09-19 14:14:28 -07:00
2019-09-29 10:00:14 -07:00
2019-09-22 09:30:30 -07:00
2019-09-24 16:31:50 -07:00
2019-09-22 09:30:30 -07:00
2019-09-23 17:20:40 -04:00
2019-09-29 10:33:41 -07:00
2019-09-24 16:31:50 -07:00
2019-09-19 13:27:23 -07:00
2019-09-23 19:16:01 -07:00
2019-09-24 12:39:40 -07:00
2019-09-27 12:19:47 -07:00
2019-09-17 18:40:42 -07:00
2019-09-22 10:55:08 -07:00
2019-09-30 10:04:28 -07:00
2019-09-22 11:05:43 -07:00
2019-09-24 16:31:50 -07:00
2019-09-16 15:52:38 -07:00
2019-09-22 10:52:23 -07:00
2019-09-17 18:40:42 -07:00
2019-09-24 15:54:08 -07:00
2019-09-24 15:54:08 -07:00
2019-09-18 11:14:31 -07:00
2019-09-23 19:33:56 -07:00
2019-09-27 11:17:38 -07:00
2019-09-26 11:22:14 -07:00
2019-09-18 11:05:34 -07:00