Biju Das 84c9829d16 clk: renesas: r9a07g043: Add clock and reset entries for ADC
Add clock and reset entries for ADC block in CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501083450.26541-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05 12:10:21 +02:00
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