Qiqi Zhang 8c11586450 drm/bridge: ti-sn65dsi86: Fix output polarity setting bug
According to the description in ti-sn65dsi86's datasheet:

CHA_HSYNC_POLARITY:
0 = Active High Pulse. Synchronization signal is high for the sync
pulse width. (default)
1 = Active Low Pulse. Synchronization signal is low for the sync
pulse width.

CHA_VSYNC_POLARITY:
0 = Active High Pulse. Synchronization signal is high for the sync
pulse width. (Default)
1 = Active Low Pulse. Synchronization signal is low for the sync
pulse width.

We should only set these bits when the polarity is negative.

Fixes: a095f15c00e2 ("drm/bridge: add support for sn65dsi86 bridge driver")
Signed-off-by: Qiqi Zhang <eddy.zhang@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20221125104558.84616-1-eddy.zhang@rock-chips.com
2022-11-30 06:40:20 -08:00
..
2022-09-26 09:11:47 +02:00
2022-10-10 13:20:53 -07:00
2022-10-05 11:24:12 -07:00
2022-10-05 11:24:12 -07:00
2022-10-10 13:59:01 -07:00
2022-08-16 12:46:26 +02:00
2022-10-05 11:24:12 -07:00
2022-10-05 11:24:12 -07:00
2022-10-05 11:24:12 -07:00
2022-10-05 10:38:24 -07:00
2022-10-05 11:24:12 -07:00
2022-09-06 10:56:04 +02:00
2022-09-20 09:37:12 +02:00
2022-10-05 11:24:12 -07:00
2022-08-26 14:22:59 +02:00
2022-07-13 10:54:56 +10:00
2022-06-28 07:56:32 +02:00
2022-03-24 16:19:43 -07:00
2022-10-05 11:24:12 -07:00
2022-09-06 10:56:04 +02:00
2022-09-06 10:56:04 +02:00
2022-10-05 11:24:12 -07:00
2022-04-12 09:27:20 +03:00
2022-10-07 17:04:10 -07:00
2022-10-07 17:04:10 -07:00