Tim Huang 27d196c449 drm/amd/pm: fix vclk setting failed for SMU v13.0.4
PMFW use the left-shifted 16 bits argument to set the VCLK
DPM frequency for SMU v13.0.4.

Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09 12:47:37 -04:00
..
2023-03-07 14:22:41 -05:00