Marcel Ziswiler 94c3847dc5 ARM: tegra: apalis-tk1: get rid of fake clocks simple bus
Get rid of the fake clocks simple bus and use node names as per the
actual schematics.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-09-26 16:50:39 +02:00
..
2018-06-15 07:55:24 +09:00
2018-04-03 15:51:22 -07:00