linux/arch/arm64/include
Catalin Marinas a41dc0e841 arm64: Implement cache_line_size() based on CTR_EL0.CWG
The hardware provides the maximum cache line size in the system via the
CTR_EL0.CWG bits. This patch implements the cache_line_size() function
to read such information, together with a sanity check if the statically
defined L1_CACHE_BYTES is smaller than the hardware value.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
2014-05-09 15:47:45 +01:00
..
asm arm64: Implement cache_line_size() based on CTR_EL0.CWG 2014-05-09 15:47:45 +01:00
uapi/asm ARM64: perf: add support for perf registers API 2014-03-13 11:22:37 +00:00