Zihao Yu ac8d0b901f riscv,entry: fix misaligned base for excp_vect_table ... In RV64, the size of each entry in excp_vect_table is 8 bytes. If the base of the table is not 8-byte aligned, loading an entry in the table will raise a misaligned exception. Although such exception will be handled by opensbi/bbl, this still causes performance degradation. Signed-off-by: Zihao Yu <yuzihao@ict.ac.cn> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2021-04-01 21:37:05 -07:00
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boot	RISC-V Patches for the 5.12 Merge Window	2021-02-26 10:28:35 -08:00
configs	RISC-V: Enable CPU Hotplug in defconfigs	2021-02-26 21:24:02 -08:00
include	riscv: evaluate put_user() arg before enabling user access	2021-04-01 21:37:04 -07:00
kernel	riscv,entry: fix misaligned base for excp_vect_table	2021-04-01 21:37:05 -07:00
lib	riscv: Add support for function error injection	2021-01-14 15:09:09 -08:00
mm	RISC-V: kasan: Declare kasan_shallow_populate() static	2021-03-16 22:01:04 -07:00
net	bpf: Rename BPF_XADD and prepare to encode other atomics in .imm	2021-01-14 18:34:29 -08:00
Kbuild	riscv: Allow device trees to be built into the kernel	2020-05-18 11:38:05 -07:00
Kconfig	riscv: Correct SPARSEMEM configuration	2021-03-16 22:15:21 -07:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.socs	riscv: Fix compilation error with Canaan SoC	2021-03-16 21:54:27 -07:00
Makefile	riscv: Enable per-task stack canaries	2021-01-14 15:09:10 -08:00