Leilk Liu adcbcfea15 spi: mediatek: fix spi clock usage error
spi clock manages flow:
  CLK_TOP_SYSPLL3_D2 ---> CLK_TOP_SPI_SEL ---> CLK_PERI_SPI0
     (source clock)           (clock mux)       (clock gate)
spi driver should choose source clock by clock mux, then enable
clock gate.

Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-31 15:26:50 +01:00
..
2015-06-16 13:08:19 +01:00
2014-12-22 15:32:42 +00:00
2015-03-25 11:54:40 -07:00
2014-12-14 16:10:09 -08:00
2015-03-17 12:15:22 +00:00
2014-12-22 15:32:42 +00:00
2015-03-17 12:15:22 +00:00
2014-12-14 16:10:09 -08:00