e0e3aca997
This is copy/pasta that breaks modular builds. Fix the match table to use the right pointer, or the right device table type. And while we're including the header, fix the order to be linux, dt-bindings, and finally local. Cc: Garmin.Chang <Garmin.Chang@mediatek.com> Cc: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Fixes:f42b9e9a43("clk: mediatek: Add MT8188 wpesys clock support") Fixes:0d2f2cefba("clk: mediatek: Add MT8188 adsp clock support") Fixes:e4aaa60eae("clk: mediatek: Add MT8188 vdosys0 clock support") Fixes:cfa4609f9b("clk: mediatek: Add MT8188 vdosys1 clock support") Fixes:bb87c1109c("clk: mediatek: Add MT8188 vencsys clock support") Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/oe-kbuild-all/202304011039.UBDX1UOT-lkp@intel.com/ Link: https://lore.kernel.org/oe-kbuild-all/202304020649.QO2HlpD5-lkp@intel.com/ Link: https://lore.kernel.org/oe-kbuild-all/202304021055.WDhQPcoS-lkp@intel.com/ Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20230404204553.1256263-1-sboyd@kernel.org
106 lines
3.9 KiB
C
106 lines
3.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Garmin Chang <garmin.chang@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/mediatek,mt8188-clk.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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static const struct mtk_gate_regs wpe_top_cg_regs = {
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.set_ofs = 0x0,
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.clr_ofs = 0x0,
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.sta_ofs = 0x0,
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};
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static const struct mtk_gate_regs wpe_vpp0_0_cg_regs = {
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.set_ofs = 0x58,
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.clr_ofs = 0x58,
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.sta_ofs = 0x58,
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};
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static const struct mtk_gate_regs wpe_vpp0_1_cg_regs = {
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.set_ofs = 0x5c,
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.clr_ofs = 0x5c,
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.sta_ofs = 0x5c,
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};
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#define GATE_WPE_TOP(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &wpe_top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
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#define GATE_WPE_VPP0_0(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &wpe_vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
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#define GATE_WPE_VPP0_1(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &wpe_vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
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static const struct mtk_gate wpe_top_clks[] = {
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GATE_WPE_TOP(CLK_WPE_TOP_WPE_VPP0, "wpe_wpe_vpp0", "top_wpe_vpp", 16),
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GATE_WPE_TOP(CLK_WPE_TOP_SMI_LARB7, "wpe_smi_larb7", "top_wpe_vpp", 18),
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GATE_WPE_TOP(CLK_WPE_TOP_WPESYS_EVENT_TX, "wpe_wpesys_event_tx", "top_wpe_vpp", 20),
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GATE_WPE_TOP(CLK_WPE_TOP_SMI_LARB7_PCLK_EN, "wpe_smi_larb7_p_en", "top_wpe_vpp", 24),
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};
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static const struct mtk_gate wpe_vpp0_clks[] = {
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/* WPE_VPP00 */
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GATE_WPE_VPP0_0(CLK_WPE_VPP0_VGEN, "wpe_vpp0_vgen", "top_img", 0),
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GATE_WPE_VPP0_0(CLK_WPE_VPP0_EXT, "wpe_vpp0_ext", "top_img", 1),
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GATE_WPE_VPP0_0(CLK_WPE_VPP0_VFC, "wpe_vpp0_vfc", "top_img", 2),
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GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH0_TOP, "wpe_vpp0_cach0_top", "top_img", 3),
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GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH0_DMA, "wpe_vpp0_cach0_dma", "top_img", 4),
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GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH1_TOP, "wpe_vpp0_cach1_top", "top_img", 5),
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GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH1_DMA, "wpe_vpp0_cach1_dma", "top_img", 6),
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GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH2_TOP, "wpe_vpp0_cach2_top", "top_img", 7),
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GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH2_DMA, "wpe_vpp0_cach2_dma", "top_img", 8),
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GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH3_TOP, "wpe_vpp0_cach3_top", "top_img", 9),
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GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH3_DMA, "wpe_vpp0_cach3_dma", "top_img", 10),
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GATE_WPE_VPP0_0(CLK_WPE_VPP0_PSP, "wpe_vpp0_psp", "top_img", 11),
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GATE_WPE_VPP0_0(CLK_WPE_VPP0_PSP2, "wpe_vpp0_psp2", "top_img", 12),
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GATE_WPE_VPP0_0(CLK_WPE_VPP0_SYNC, "wpe_vpp0_sync", "top_img", 13),
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GATE_WPE_VPP0_0(CLK_WPE_VPP0_C24, "wpe_vpp0_c24", "top_img", 14),
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GATE_WPE_VPP0_0(CLK_WPE_VPP0_MDP_CROP, "wpe_vpp0_mdp_crop", "top_img", 15),
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GATE_WPE_VPP0_0(CLK_WPE_VPP0_ISP_CROP, "wpe_vpp0_isp_crop", "top_img", 16),
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GATE_WPE_VPP0_0(CLK_WPE_VPP0_TOP, "wpe_vpp0_top", "top_img", 17),
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/* WPE_VPP0_1 */
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GATE_WPE_VPP0_1(CLK_WPE_VPP0_VECI, "wpe_vpp0_veci", "top_img", 0),
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GATE_WPE_VPP0_1(CLK_WPE_VPP0_VEC2I, "wpe_vpp0_vec2i", "top_img", 1),
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GATE_WPE_VPP0_1(CLK_WPE_VPP0_VEC3I, "wpe_vpp0_vec3i", "top_img", 2),
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GATE_WPE_VPP0_1(CLK_WPE_VPP0_WPEO, "wpe_vpp0_wpeo", "top_img", 3),
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GATE_WPE_VPP0_1(CLK_WPE_VPP0_MSKO, "wpe_vpp0_msko", "top_img", 4),
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};
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static const struct mtk_clk_desc wpe_top_desc = {
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.clks = wpe_top_clks,
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.num_clks = ARRAY_SIZE(wpe_top_clks),
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};
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static const struct mtk_clk_desc wpe_vpp0_desc = {
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.clks = wpe_vpp0_clks,
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.num_clks = ARRAY_SIZE(wpe_vpp0_clks),
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};
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static const struct of_device_id of_match_clk_mt8188_wpe[] = {
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{ .compatible = "mediatek,mt8188-wpesys", .data = &wpe_top_desc },
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{ .compatible = "mediatek,mt8188-wpesys-vpp0", .data = &wpe_vpp0_desc },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_wpe);
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static struct platform_driver clk_mt8188_wpe_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8188-wpe",
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.of_match_table = of_match_clk_mt8188_wpe,
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},
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};
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module_platform_driver(clk_mt8188_wpe_drv);
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MODULE_LICENSE("GPL");
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