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The adc_clk variable is currently defined using a 32-bits unsigned integer,
which will overflow under some very valid range of operations.
Such overflow will occur if, for example, the parent clock is set to a
20MHz frequency and the ADC startup time is larger than 215ns.
To fix this, introduce an intermediate variable holding the clock rate
in kHz.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
db10e20117