c0a636e4cc
The main PLL calculation has a mistake. We should be using the
multiplying the VCO frequency, not the parent clock frequency.
Fixes:
|
||
|---|---|---|
| .. | ||
| clk-gate-a10.c | ||
| clk-gate-s10.c | ||
| clk-gate.c | ||
| clk-periph-a10.c | ||
| clk-periph-s10.c | ||
| clk-periph.c | ||
| clk-pll-a10.c | ||
| clk-pll-s10.c | ||
| clk-pll.c | ||
| clk-s10.c | ||
| clk.c | ||
| clk.h | ||
| Makefile | ||
| stratix10-clk.h | ||