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Intel perf LBR
- A CFI fix to ftrace along with a simplification
- Adjust handling of zero capacity bit mask for resctrl cache allocation
on AMD
- A fix to the AMD microcode loader to attempt patch application on
every logical thread
- A couple of topology fixes to handle CPUID leaf 0x1f enumeration info
properly
- Drop a -mabi=ms compiler option check as both compilers support it now
anyway
- A couple of fixes to how the initial, statically allocated FPU buffer
state is setup and its interaction with dynamic states at runtime
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmNVCj4ACgkQEsHwGGHe
VUoalw//WV4aEXgJx6Zz4PoawE1zeAFa4LlrDZDpZ8HxdcT0yXr9MNMIn4qN3j4H
xsc/MWrdEWWS0rmt//IWzI3ee+VYTnrLjkBajQcNJ9qmqGJaS0ooKm9+j2eWG8J5
ZRLTx5+jJhoEkyYhDQvTXeSGLMjs+X/3Y6CXKzDKaIA5PVqMsc2lxa70MwsjKoVm
7XqFHmmv3Vw9JmmqsLBRp+VmYzNlgZ9eqaD+pujiYnz7h8fHYyN2I6LhNIYpoHHr
gUY0LwxjqJ9O+CaF2fsTDH6oDevVMt5qGntzsa1hx09gO6UzgZwTr+Sme74zE3ox
Lj3IDj/EuxCNIeCByHpmvVOdKnvEEsx6+BDAuiq+EPSDykPUHmp1fiDywR1TC9o0
PwQ06+/AbXtbKA0JOb1ArFlBB+aE2W7r+Rj8yH3UpsLjDh7sKM0kERm9RuFw7aKJ
j35y9mzvJtR3fstb5MD9rI0lBEL6p5JIQSZvulWqf5l5h0K2DS/7OYGJu2GPjU+c
PFA+tnGgs0vc98w2clBzQVk5Yo9gJCma5eGUy8bJ/ESwTfBzERBTscD53kT7jyWn
TW4nMSkr1H4aR7dXjb5suhSo1IqDMtFAWPECh0f6btgTzf5JOeS2dCihGHRbmh8z
5ByhZHdg8tJiX0xBv1s31KGZECQQxCy8AJr3MXKxOjqjXoI4fFg=
=2hxy
-----END PGP SIGNATURE-----
Merge tag 'x86_urgent_for_v6.0_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Borislav Petkov:
"As usually the case, right after a major release, the tip urgent
branches accumulate a couple more fixes than normal. And here is the
x86, a bit bigger, urgent pile.
- Use the correct CPU capability clearing function on the error path
in Intel perf LBR
- A CFI fix to ftrace along with a simplification
- Adjust handling of zero capacity bit mask for resctrl cache
allocation on AMD
- A fix to the AMD microcode loader to attempt patch application on
every logical thread
- A couple of topology fixes to handle CPUID leaf 0x1f enumeration
info properly
- Drop a -mabi=ms compiler option check as both compilers support it
now anyway
- A couple of fixes to how the initial, statically allocated FPU
buffer state is setup and its interaction with dynamic states at
runtime"
* tag 'x86_urgent_for_v6.0_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/fpu: Fix copy_xstate_to_uabi() to copy init states correctly
perf/x86/intel/lbr: Use setup_clear_cpu_cap() instead of clear_cpu_cap()
ftrace,kcfi: Separate ftrace_stub() and ftrace_stub_graph()
x86/ftrace: Remove ftrace_epilogue()
x86/resctrl: Fix min_cbm_bits for AMD
x86/microcode/AMD: Apply the patch early on every logical thread
x86/topology: Fix duplicated core ID within a package
x86/topology: Fix multiple packages shown on a single-package system
hwmon/coretemp: Handle large core ID value
x86/Kconfig: Drop check for -mabi=ms for CONFIG_EFI_STUB
x86/fpu: Exclude dynamic states from init_fpstate
x86/fpu: Fix the init_fpstate size check with the actual size
x86/fpu: Configure init_fpstate attributes orderly
295dad10bf